On 6/3/19 1:13 PM, Paul E. McKenney wrote: > On Mon, Jun 03, 2019 at 06:08:35PM +0000, Vineet Gupta wrote: >> On 5/31/19 1:21 AM, Peter Zijlstra wrote: >>>> I'm not sure how to interpret "natural alignment" for the case of double >>>> load/stores on 32-bit systems where the hardware and ABI allow for 4 byte >>>> alignment (ARCv2 LDD/STD, ARM LDRD/STRD ....) >>> Natural alignment: !((uintptr_t)ptr % sizeof(*ptr)) >>> >>> For any u64 type, that would give 8 byte alignment. the problem >>> otherwise being that your data spans two lines/pages etc.. >> Sure, but as Paul said, if the software doesn't expect them to be atomic by >> default, they could span 2 hardware lines to keep the implementation >> simpler/sane. > I could imagine 8-byte types being only four-byte aligned on 32-bit systems, > but it would be quite a surprise on 64-bit systems.
Totally agree ! Thx, -Vineet
