Fix the compiler warning with ARM64 config enabled
as the current mask assumes 32 bit by default.

Signed-off-by: Keerthy <j-keer...@ti.com>
---
 drivers/gpio/gpio-davinci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index 3bbf5804bd11..0977590eb996 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -297,7 +297,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 static void gpio_irq_disable(struct irq_data *d)
 {
        struct davinci_gpio_regs __iomem *g = irq2regs(d);
-       u32 mask = (u32) irq_data_get_irq_handler_data(d);
+       uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
 
        writel_relaxed(mask, &g->clr_falling);
        writel_relaxed(mask, &g->clr_rising);
@@ -306,7 +306,7 @@ static void gpio_irq_disable(struct irq_data *d)
 static void gpio_irq_enable(struct irq_data *d)
 {
        struct davinci_gpio_regs __iomem *g = irq2regs(d);
-       u32 mask = (u32) irq_data_get_irq_handler_data(d);
+       uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
        unsigned status = irqd_get_trigger_type(d);
 
        status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
@@ -447,7 +447,7 @@ davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
                                "davinci_gpio");
        irq_set_irq_type(irq, IRQ_TYPE_NONE);
        irq_set_chip_data(irq, (__force void *)g);
-       irq_set_handler_data(irq, (void *)__gpio_mask(hw));
+       irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
 
        return 0;
 }
-- 
2.17.1

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