On Mon, Jun 03, 2019 at 09:50:20AM +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang <anson.hu...@nxp.com>
>
> GIC is inside of SoC from architecture perspective, it should
> be located inside of soc node in DT.
>
> Signed-off-by: Anson Huang <anson.hu...@nxp.com>
It doesn't apply to my imx/dt64 branch. Please generate it against that
branch for my for-next.
Shawn
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index dc99f45..429312e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -169,15 +169,6 @@
> clock-output-names = "clk_ext4";
> };
>
> - gic: interrupt-controller@38800000 {
> - compatible = "arm,gic-v3";
> - reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
> - <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base)
> */
> - #interrupt-cells = <3>;
> - interrupt-controller;
> - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> psci {
> compatible = "arm,psci-1.0";
> method = "smc";
> @@ -739,6 +730,15 @@
> dma-names = "rx-tx";
> status = "disabled";
> };
> +
> + gic: interrupt-controller@38800000 {
> + compatible = "arm,gic-v3";
> + reg = <0x38800000 0x10000>, /* GIC Dist */
> + <0x38880000 0xc0000>; /* GICR (RD_base +
> SGI_base) */
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> usbphynop1: usbphynop1 {
> --
> 2.7.4
>
