Am Mittwoch, 5. Juni 2019, 00:31:59 CEST schrieb Douglas Anderson: > The 48 MHz PLL rate is not present in the downstream chromeos-3.14 > tree. Looking at history, it was originally removed in > <https://crrev.com/c/265810> ("CHROMIUM: clk: rockchip: expand more > clocks support") with no explanation. Much of that patch was later > reverted in <https://crrev.com/c/284595> ("CHROMIUM: clk: rockchip: > Revert more questionable PLL rates"), but that patch left in the > removal of 48 MHz. What I wrote in that patch: > > > Note that the original change also removed the rate (48000000, 1, > > 64, 32) from the table. I have no idea why that was squashed in > > there, but that rate was invalid anyway (it appears to have an out > > of bounds NO). I'm not putting that rate in. > > Reading the TRM I see that NO is defined as > - NO: 1, 2-16 (even only) > ...and furthermore only 4 bits are assigned for NO-1, which means that > the highest NO we could even represent is 16. > > Signed-off-by: Douglas Anderson <diand...@chromium.org>
applied for 5.3 Thanks Heiko
