On Wed, May 22, 2019 at 11:33:49PM +0200, Remi Pommarel wrote:
> PCI_EXP_RTCTL is used to activate PME interrupt only, so writing into it
> should not modify other interrupts' mask (such as ISR0).
>
> Fixes: 6302bf3ef78d ("PCI: Init PCIe feature bits for managed host bridge
> alloc")
> Signed-off-by: Remi Pommarel <r...@triplefau.lt>
> ---
> Please note that I will unlikely be able to answer any comments from May
> 24th to June 10th.
> ---
> drivers/pci/controller/pci-aardvark.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pci-aardvark.c
> b/drivers/pci/controller/pci-aardvark.c
> index 134e0306ff00..27102d3b4f9c 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -451,10 +451,14 @@ advk_pci_bridge_emul_pcie_conf_write(struct
> pci_bridge_emul *bridge,
> advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
> break;
>
> - case PCI_EXP_RTCTL:
> - new = (new & PCI_EXP_RTCTL_PMEIE) << 3;
> - advk_writel(pcie, new, PCIE_ISR0_MASK_REG);
> + case PCI_EXP_RTCTL: {
> + /* Only mask/unmask PME interrupt */
> + u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
> + ~PCIE_MSG_PM_PME_MASK;
> + val |= (new & PCI_EXP_RTCTL_PMEIE) << 3;
I know you have not introduced this code but maybe we can
take an opportunity to clarify it (that << 3 shift obfuscates
a bit):
u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
~PCIE_MSG_PM_PME_MASK;
if (new & PCI_EXP_RTCTL_PMEIE)
val |= PCIE_MSG_PM_PME_MASK;
advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
break;
Or I am not reading the code correctly ?
Regardless, I need Thomas' ACK to proceed.
Lorenzo
> + advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
> break;
> + }
>
> case PCI_EXP_RTSTA:
> new = (new & PCI_EXP_RTSTA_PME) >> 9;
> --
> 2.20.1
>
