On Fri, Jun 14, 2019 at 02:35:53PM -0400, Shravan Kumar Ramani wrote:
> Add ECC support for Mellanox BlueField SoC DDR controller.
> This requires SMC to the running Arm Trusted Firmware to report
> what is the current memory configuration.
>
> Signed-off-by: Shravan Kumar Ramani <sram...@mellanox.com>
> ---
> MAINTAINERS | 5 +
> drivers/edac/Kconfig | 7 +
> drivers/edac/Makefile | 1 +
> drivers/edac/bluefield_edac.c | 404
> ++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 417 insertions(+)
> create mode 100644 drivers/edac/bluefield_edac.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 57f496c..9d04cc4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5669,6 +5669,11 @@ S: Supported
> F: drivers/edac/aspeed_edac.c
> F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
>
> +EDAC-BLUEFIELD
> +M: Shravan Kumar Ramani <sram...@mellanox.com>
> +S: Supported
> +F: drivers/edac/bluefield_edac.c
> +
> EDAC-CALXEDA
> M: Robert Richter <r...@kernel.org>
> L: linux-e...@vger.kernel.org
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 5e2e034..43df551 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -504,4 +504,11 @@ config EDAC_ASPEED
> First, ECC must be configured in the bootloader. Then, this driver
> will expose error counters via the EDAC kernel framework.
>
> +config EDAC_BLUEFIELD
> + tristate "Mellanox BlueField Memory ECC"
> + depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
> + help
> + Support for error detection and correction on the
> + Mellanox BlueField SoCs.
> +
> endif # EDAC
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index 89ad4a84..0294a67 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -84,3 +84,4 @@ obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
> obj-$(CONFIG_EDAC_TI) += ti_edac.o
> obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o
> obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o
> +obj-$(CONFIG_EDAC_BLUEFIELD) += bluefield_edac.o
> diff --git a/drivers/edac/bluefield_edac.c b/drivers/edac/bluefield_edac.c
> new file mode 100644
> index 0000000..9c69033
> --- /dev/null
> +++ b/drivers/edac/bluefield_edac.c
> @@ -0,0 +1,404 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Bluefield-specific EDAC driver.
> + *
> + * Copyright (c) 2019 Mellanox Technologies.
> + */
> +
> +#include <linux/acpi.h>
> +#include <linux/arm-smccc.h>
> +#include <linux/edac.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "edac_module.h"
> +
> +#define DRIVER_NAME "bluefield-edac"
> +
> +/*
> + * Mellanox BlueField EMI (External Memory Interface) register definitions.
> + */
> +
> +#define MLXBF_EMI_DRAM_ECC_COUNT 0x340
> +#define MLXBF_EMI_DRAM_ECC_COUNT__LENGTH 0x0001
> +
> +#define MLXBF_EMI_DRAM_ECC_COUNT__SINGLE_ERROR_COUNT_SHIFT 0
> +#define MLXBF_EMI_DRAM_ECC_COUNT__SINGLE_ERROR_COUNT_RMASK 0xffff
> +
> +#define MLXBF_EMI_DRAM_ECC_COUNT__DOUBLE_ERROR_COUNT_SHIFT 16
> +#define MLXBF_EMI_DRAM_ECC_COUNT__DOUBLE_ERROR_COUNT_RMASK 0xffff
> +
> +#define MLXBF_EMI_DRAM_ECC_ERROR 0x348
> +
> +#define MLXBF_EMI_DRAM_ECC_ERROR__DRAM_ECC_SINGLE_SHIFT 0
> +#define MLXBF_EMI_DRAM_ECC_ERROR__DRAM_ECC_SINGLE_RMASK 0x1
> +
> +#define MLXBF_EMI_DRAM_ECC_ERROR__DRAM_ECC_DOUBLE_SHIFT 16
> +#define MLXBF_EMI_DRAM_ECC_ERROR__DRAM_ECC_DOUBLE_RMASK 0x1
> +
> +#define MLXBF_EMI_DRAM_ECC_LATCH_SELECT 0x354
> +
> +#define MLXBF_EMI_DRAM_ECC_LATCH_SELECT__DRAM_ECC_FIRST_SHIFT 0
> +#define MLXBF_EMI_DRAM_ECC_LATCH_SELECT__DRAM_ECC_FIRST_RMASK 0x1
> +
> +#define MLXBF_EMI_DRAM_ECC_LATCH_SELECT__EDGE_SEL_SHIFT 16
> +#define MLXBF_EMI_DRAM_ECC_LATCH_SELECT__EDGE_SEL_RMASK 0xf
> +
> +#define MLXBF_EMI_DRAM_ECC_LATCH_SELECT__START_SHIFT 24
> +#define MLXBF_EMI_DRAM_ECC_LATCH_SELECT__START_RMASK 0x1
> +
> +#define MLXBF_EMI_DRAM_ERR_ADDR_0 0x358
> +
> +#define MLXBF_EMI_DRAM_ERR_ADDR_1 0x37c
> +
> +#define MLXBF_EMI_DRAM_SYNDROM 0x35c
> +#define MLXBF_EMI_DRAM_SYNDROM__LENGTH 0x0001
> +
> +#define MLXBF_EMI_DRAM_SYNDROM__DERR_SHIFT 0
> +#define MLXBF_EMI_DRAM_SYNDROM__DERR_RMASK 0x1
> +
> +#define MLXBF_EMI_DRAM_SYNDROM__SERR_SHIFT 1
> +#define MLXBF_EMI_DRAM_SYNDROM__SERR_RMASK 0x1
> +
> +#define MLXBF_EMI_DRAM_SYNDROM__SYNDROM_SHIFT 16
> +#define MLXBF_EMI_DRAM_SYNDROM__SYNDROM_RMASK 0x3ff
> +
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0 0x364
> +
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0__ERR_BANK_SHIFT 0
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0__ERR_BANK_RMASK 0xf
> +
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0__ERR_LRANK_SHIFT 4
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0__ERR_LRANK_RMASK 0x3
> +
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0__ERR_PRANK_SHIFT 8
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0__ERR_PRANK_RMASK 0x3
> +
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0__ERR_EDGE_SHIFT 16
> +#define MLXBF_EMI_DRAM_ADDITIONAL_INFO_0__ERR_EDGE_RMASK 0xff
So those are *excessively* long macro names. So long that they impair
reading the code properly. Please shorten excessively.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
