Hello Tao,
Let me more clear. When you set (3, 15, 14) the device sometimes
response nack.
but when you set (4, 7, 7), the device always ack. Am I right?
Ryan
-----Original Message-----
From: Tao Ren [mailto:[email protected]]
Sent: Thursday, June 20, 2019 3:57 PM
To: Ryan Chen <[email protected]>; Brendan Higgins
<[email protected]>
Cc: Mark Rutland <[email protected]>; devicetree
<[email protected]>; [email protected]; OpenBMC Maillist
<[email protected]>; Linux Kernel Mailing List
<[email protected]>; Rob Herring <[email protected]>; Linux ARM
<[email protected]>; [email protected]
Subject: Re: [PATCH 1/2] i2c: aspeed: allow to customize base clock divisor
On 6/20/19 12:29 AM, Ryan Chen wrote:
> Hello Tao,
> Our recommend about clk divider setting is follow the datasheet clock
> setting table for clock divisor.
>
> Ryan
Thanks Ryan for the response. Could you also share some recommendations/hints
on how to solve the intermittent i2c transaction failures on Facebook AST2500
BMC platforms?
BTW, the patch is not aimed at modifying the existing formula of calculating
clock settings in i2c-aspeed driver: people still get the recommended settings
by default. The goal of the patch is to allow people to customize clock
settings in case the default/recommended one doesn't work.
Cheers,
Tao
