On Mon, Jun 24, 2019 at 08:23:33PM +0200, Maxime Ripard wrote:
> On Sun, Jun 23, 2019 at 12:42:03PM -0400, Yangtao Li wrote:
> > H3 has extra clock, so introduce something in ths_thermal_chip/ths_device
> > and adds the process of the clock.
> >
> > This is pre-work for supprt it.
> >
> > Signed-off-by: Yangtao Li <tiny.win...@gmail.com>
> > ---
> > drivers/thermal/sun8i_thermal.c | 17 ++++++++++++++++-
> > 1 file changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/thermal/sun8i_thermal.c
> > b/drivers/thermal/sun8i_thermal.c
> > index ed1c19bb27cf..04f53ffb6a14 100644
> > --- a/drivers/thermal/sun8i_thermal.c
> > +++ b/drivers/thermal/sun8i_thermal.c
> > @@ -54,6 +54,7 @@ struct tsensor {
> > };
> >
> > struct ths_thermal_chip {
> > + bool has_ahb_clk;
> > int sensor_num;
> > int offset;
> > int scale;
> > @@ -69,6 +70,7 @@ struct ths_device {
> > struct regmap *regmap;
> > struct reset_control *reset;
> > struct clk *bus_clk;
> > + struct clk *ahb_clk;
>
> Hmm, thinking a bit about this, the name of those two clocks doesn't
> make sense. AHB is the bus being used to access that device, so the
> bus clock is the AHB clock.
>
> What is that clock being used for?
To control the A/D and sample averaging logic, I suppose. It's controlled by the
THS_CLK_REG (THS Clock Register) in H3 user manual.
bus_clk controls THS_GATING in BUS_CLK_GATING_REG2 (THS module is connected to
APB bus).
I'd call it ths_clk and bus_clk.
regards,
o.
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>
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