From: Anson Huang <anson.hu...@nxp.com>
i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/clk/imx/clk-imx8mm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 516e68d..d1a84f7 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] = {"osc_24m",
"sys_pll2_100m", "sys_pll1_1
"sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m",
"sys_pll1_400m", "sys_pll1_40m",
- "video_pll1_out", "sys_pll1_800m",
"audio_pll1_out", "clk_ext1" };
+ "video_pll1_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1" };
static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m",
"sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m", };
--
2.7.4
