Linus, The following changes since commit 4b972a01a7da614b4796475f933094751a295a2f:
Linux 5.2-rc6 (2019-06-22 16:01:36 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-v5.2/fixes-rc7 for you to fetch changes up to 0db7f5cd4aeba4cc63d0068598b3350eba8bb4cd: riscv: mm: Fix code comment (2019-06-26 15:10:30 -0700) ---------------------------------------------------------------- Minor RISC-V fixes and one defconfig update for the v5.2-rc series. The fixes have no functional impact: - Fix some comment text in the memory management vmalloc_fault path. - Fix some warnings from the DT compiler in our newly-added DT files. - Change the newly-added DT bindings such that SoC IP blocks with external I/O are marked as "disabled" by default, then enable them explicitly in board DT files when the devices are used on the board. This aligns the bindings with existing upstream practice. - Add the MIT license as an option for a minor header file, at the request of one of the U-Boot maintainers. The RISC-V defconfig update builds the SiFive SPI driver and the MMC-SPI driver by default. The intention here is to make v5.2 more usable for testers and users with RISC-V hardware. ---------------------------------------------------------------- Atish Patra (1): RISC-V: defconfig: enable MMC & SPI for RISC-V Paul Walmsley (2): dt-bindings: riscv: resolve 'make dt_binding_check' warnings dt-bindings: clock: sifive: add MIT license as an option for the header file ShihPo Hung (1): riscv: mm: Fix code comment Yash Shah (1): riscv: dts: Re-organize the DT nodes Documentation/devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++++---------- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 6 +++++ .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 13 +++++++++++ arch/riscv/configs/defconfig | 5 +++++ arch/riscv/mm/fault.c | 3 --- include/dt-bindings/clock/sifive-fu540-prci.h | 2 +- 6 files changed, 39 insertions(+), 16 deletions(-)