Hi Neil, On Mon, Jul 1, 2019 at 12:49 PM Neil Armstrong <narmstr...@baylibre.com> wrote: > > Add the clk-measurer clocks IDs for the Amlogic SM1 SoC family. > > Signed-off-by: Neil Armstrong <narmstr...@baylibre.com> > --- > drivers/soc/amlogic/meson-clk-measure.c | 134 ++++++++++++++++++++++++ > 1 file changed, 134 insertions(+) > > diff --git a/drivers/soc/amlogic/meson-clk-measure.c > b/drivers/soc/amlogic/meson-clk-measure.c > index f09b404b39d3..e32e97613000 100644 > --- a/drivers/soc/amlogic/meson-clk-measure.c > +++ b/drivers/soc/amlogic/meson-clk-measure.c > @@ -357,6 +357,136 @@ static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { > CLK_MSR_ID(122, "audio_pdm_dclk"), > }; > > +static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = { > + CLK_MSR_ID(0, "ring_osc_out_ee_0"), > + CLK_MSR_ID(1, "ring_osc_out_ee_1"), > + CLK_MSR_ID(2, "ring_osc_out_ee_2"), > + CLK_MSR_ID(3, "ring_osc_out_ee_3"), > + CLK_MSR_ID(4, "gp0_pll"), > + CLK_MSR_ID(5, "gp1_pll"), > + CLK_MSR_ID(6, "enci"), > + CLK_MSR_ID(7, "clk81"), > + CLK_MSR_ID(8, "encp"), > + CLK_MSR_ID(9, "encl"), > + CLK_MSR_ID(10, "vdac"), > + CLK_MSR_ID(11, "eth_tx"), > + CLK_MSR_ID(12, "hifi_pll"), > + CLK_MSR_ID(13, "mod_tcon"), > + CLK_MSR_ID(14, "fec_0"), > + CLK_MSR_ID(15, "fec_1"), > + CLK_MSR_ID(16, "fec_2"), > + CLK_MSR_ID(17, "sys_pll_div16"), > + CLK_MSR_ID(18, "sys_cpu_div16"), > + CLK_MSR_ID(19, "lcd_an_ph2"), > + CLK_MSR_ID(20, "rtc_osc_out"), > + CLK_MSR_ID(21, "lcd_an_ph3"), > + CLK_MSR_ID(22, "eth_phy_ref"), > + CLK_MSR_ID(23, "mpll_50m"), > + CLK_MSR_ID(24, "eth_125m"), > + CLK_MSR_ID(25, "eth_rmii"), > + CLK_MSR_ID(26, "sc_int"), > + CLK_MSR_ID(27, "in_mac"), > + CLK_MSR_ID(28, "sar_adc"), > + CLK_MSR_ID(29, "pcie_inp"), > + CLK_MSR_ID(30, "pcie_inn"), > + CLK_MSR_ID(31, "mpll_test_out"), > + CLK_MSR_ID(32, "vdec"), > + CLK_MSR_ID(34, "eth_mpll_50m"), > + CLK_MSR_ID(35, "mali"), > + CLK_MSR_ID(36, "hdmi_tx_pixel"), > + CLK_MSR_ID(37, "cdac"), > + CLK_MSR_ID(38, "vdin_meas"), > + CLK_MSR_ID(39, "bt656"), > + CLK_MSR_ID(40, "arm_ring_osc_out_4"), > + CLK_MSR_ID(41, "eth_rx_or_rmii"), > + CLK_MSR_ID(42, "mp0_out"), > + CLK_MSR_ID(43, "fclk_div5"), > + CLK_MSR_ID(44, "pwm_b"), > + CLK_MSR_ID(45, "pwm_a"), > + CLK_MSR_ID(46, "vpu"), > + CLK_MSR_ID(47, "ddr_dpll_pt"), > + CLK_MSR_ID(48, "mp1_out"), > + CLK_MSR_ID(49, "mp2_out"), > + CLK_MSR_ID(50, "mp3_out"), > + CLK_MSR_ID(51, "sd_emmc_c"), > + CLK_MSR_ID(52, "sd_emmc_b"), > + CLK_MSR_ID(53, "sd_emmc_a"), > + CLK_MSR_ID(54, "vpu_clkc"), > + CLK_MSR_ID(55, "vid_pll_div_out"), > + CLK_MSR_ID(56, "wave420l_a"), > + CLK_MSR_ID(57, "wave420l_c"), > + CLK_MSR_ID(58, "wave420l_b"), > + CLK_MSR_ID(59, "hcodec"), > + CLK_MSR_ID(40, "arm_ring_osc_out_5"), is this index 40 or 60?
> + CLK_MSR_ID(61, "gpio_msr"), > + CLK_MSR_ID(62, "hevcb"), > + CLK_MSR_ID(63, "dsi_meas"), > + CLK_MSR_ID(64, "spicc_1"), > + CLK_MSR_ID(65, "spicc_0"), > + CLK_MSR_ID(66, "vid_lock"), > + CLK_MSR_ID(67, "dsi_phy"), > + CLK_MSR_ID(68, "hdcp22_esm"), > + CLK_MSR_ID(69, "hdcp22_skp"), > + CLK_MSR_ID(70, "pwm_f"), > + CLK_MSR_ID(71, "pwm_e"), > + CLK_MSR_ID(72, "pwm_d"), > + CLK_MSR_ID(73, "pwm_c"), > + CLK_MSR_ID(74, "arm_ring_osc_out_6"), > + CLK_MSR_ID(75, "hevcf"), > + CLK_MSR_ID(74, "arm_ring_osc_out_7"), is this index 74 or 76?