This patch changes speed and parent of NoC WCORE bus to 400MHz. The clock is now attached to a branch were the root is the DPLL which speed is set to 1200MHz. The OPPs are aligned to this rate accordingly.
Signed-off-by: Lukasz Luba <[email protected]> --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25d95de15c9b..aaf18653d8ac 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -46,6 +46,13 @@ <&nocp_mem1_0>, <&nocp_mem1_1>; vdd-supply = <&buck3_reg>; exynos,saturation-ratio = <100>; + assigned-clocks = <&clock CLK_MOUT_ACLK400_WCORE>, + <&clock CLK_MOUT_SW_ACLK400_WCORE>, + <&clock CLK_DOUT_ACLK400_WCORE>, + <&clock CLK_FOUT_DPLL>; + assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>, + <&clock CLK_DOUT_ACLK400_WCORE>; + assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>; status = "okay"; }; -- 2.17.1
