[PATCH 2/3] arm64: dts: imx8qxp: Add DSP DT node

[Daniel Baluta]

This includes DSP reserved memory, ADMA DSP device and DSP MU
communication channels description.

Signed-off-by: Daniel Baluta <daniel.bal...@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts |  4 +++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi    | 32 +++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts 
b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index bfdada2db176..19468058e6ae 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -230,3 +230,7 @@
                >;
        };
 };
+
+&adma_dsp {
+       status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi 
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 05fa0b7f36bb..6a4efb1f0fa2 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -113,6 +113,17 @@
                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               dsp_reserved: dsp@92400000 {
+                       reg = <0 0x92400000 0 0x2000000>;
+                       no-map;
+               };
+       };
+
        pmu {
                compatible = "arm,armv8-pmuv3";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -204,6 +215,27 @@
                        #clock-cells = <1>;
                };
 
+               adma_dsp: dsp@596e8000 {
+                       compatible = "fsl,imx8qxp-dsp";
+                       reg = <0x596e8000 0x88000>;
+                       clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
+                               <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
+                               <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
+                       clock-names = "ipg", "ocram", "core";
+                       power-domains = <&pd IMX_SC_R_MU_13A>,
+                               <&pd IMX_SC_R_MU_13B>,
+                               <&pd IMX_SC_R_DSP>,
+                               <&pd IMX_SC_R_DSP_RAM>;
+                       mbox-names = "txdb0", "txdb1",
+                               "rxdb0", "rxdb1";
+                       mboxes = <&lsio_mu13 2 0>,
+                               <&lsio_mu13 2 1>,
+                               <&lsio_mu13 3 0>,
+                               <&lsio_mu13 3 1>;
+                       reserved-region = <&dsp_reserved>;
+                       status = "disabled";
+               };
+
                adma_lpuart0: serial@5a060000 {
                        compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
                        reg = <0x5a060000 0x1000>;
-- 
2.17.1