On Mon, Jul 15, 2019 at 02:55:43AM +0000, Peng Fan wrote:
> From: Peng Fan <peng....@nxp.com>
>
> The AUDIO PLL max support 650M, so the original clk settings violate
> spec. This patch makes the output 786432000 -> 393216000,
> and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
> impact on audio functionality and go within 650MHz PLL limit.
>
> Cc: <sta...@vger.kernel.org>
> Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
> Signed-off-by: Peng Fan <peng....@nxp.com>
Applied, thanks.
