On Mon, Jul 29, 2019 at 2:19 AM Andrew Jeffery <[email protected]> wrote:
> The behaviour is to periodically emit the state of all enabled GPIOs > (i.e. the ngpios value), one per bus clock cycle. There's no explicit > addressing scheme, the protocol encodes the value for a given GPIO > by its position in the data stream relative to a pulse on the "load data" > (LD) line, whose envelope covers the clock cycle for the last GPIO in > the sequence. Similar to SPI the bus has both out and in lines, which > cater to output/input GPIOs. > > A rough timing diagram for a 16-GPIO configuration looks like what > I've pasted here: > > https://gist.github.com/amboar/c9543af1957854474b8c05ab357f0675 OK that is complex. I agree we need to keep this driver together. Yours, Linus Walleij
