On 31/07/19 03:55, Atish Patra wrote:
> On Tue, 2019-07-30 at 13:26 +0200, Paolo Bonzini wrote:
>> On 29/07/19 13:57, Anup Patel wrote:
>>> + if (delta_ns > VCPU_TIMER_PROGRAM_THRESHOLD_NS) {
>>> + hrtimer_start(&t->hrt, ktime_add_ns(ktime_get(),
>>> delta_ns),
>>
>> I think the guest would prefer if you saved the time before enabling
>> interrupts on the host, and use that here instead of ktime_get().
>> Otherwise the timer could be delayed arbitrarily by host interrupts.
>>
>> (Because the RISC-V SBI timer is relative only---which is
>> unfortunate---
>
> Just to clarify: RISC-V SBI timer call passes absolute time.
>
> https://elixir.bootlin.com/linux/v5.3-rc2/source/drivers/clocksource/timer-riscv.c#L32
>
> That's why we compute a delta between absolute time passed via SBI and
> current time. hrtimer is programmed to trigger only after the delta
> time from now.
Nevermind, I got lost in all the conversions.
One important issue is the lack of ability to program a delta between
HS/HU-mode cycles and VS/VU-mode cycles. Without this, it's impossible
to do virtual machine migration (except with hcounteren
trap-and-emulate, which I think we agree is not acceptable). I found
the open issue at https://github.com/riscv/riscv-isa-manual/issues/298
and commented on it.
Paolo
