On Fri, Aug 02, 2019 at 08:33:58PM -0400, Qian Cai wrote:
> The commit d5370f754875 ("arm64: prefetch: add alternative pattern for
> CPUs without a prefetcher") introduced MIDR_IS_CPU_MODEL_RANGE() to be
> used in has_no_hw_prefetch() with rv_min=0 which generates a compilation
> warning from GCC,
>
> In file included from ./arch/arm64/include/asm/cache.h:8,
> from ./include/linux/cache.h:6,
> from ./include/linux/printk.h:9,
> from ./include/linux/kernel.h:15,
> from ./include/linux/cpumask.h:10,
> from arch/arm64/kernel/cpufeature.c:11:
> arch/arm64/kernel/cpufeature.c: In function 'has_no_hw_prefetch':
> ./arch/arm64/include/asm/cputype.h:59:26: warning: comparison of
> unsigned expression >= 0 is always true [-Wtype-limits]
> _model == (model) && rv >= (rv_min) && rv <= (rv_max); \
> ^~
> arch/arm64/kernel/cpufeature.c:889:9: note: in expansion of macro
> 'MIDR_IS_CPU_MODEL_RANGE'
> return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
> ^~~~~~~~~~~~~~~~~~~~~~~
>
> Fix it by making "rv" a "s32".
>
> Signed-off-by: Qian Cai <c...@lca.pw>
> ---
>
> v2: Use "s32" for "rv", so "variant 0/revision 0" can be covered.
>
> arch/arm64/include/asm/cputype.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/cputype.h
> b/arch/arm64/include/asm/cputype.h
> index e7d46631cc42..d52fe8651c2d 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -54,7 +54,7 @@
> #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \
> ({ \
> u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \
> - u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \
> + s32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \
Hmm, but this really isn't a signed quantity: it's two fields extracted
from an ID register. I think the code is fine. Are you explicitly enabling
-Wtype-limits somehow?
Will
