On Wed, Aug 07, 2019 at 06:10:09PM +0300, Christoph Hellwig wrote:
> The sifive_l2_cache.c is in no way related to RISC-V architecture
> memory management. It is a little stub driver working around the fact
> that the EDAC maintainers prefer their drivers to be structured in a
> certain way that doesn't fit the SiFive SOCs.
>
> Move the file to drivers/misc and only build it when the EDAC_SIFIVE
> config option is selected.
>
> Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver
> for SiFive SoCs")
> Signed-off-by: Christoph Hellwig <h...@lst.de>
> ---
> arch/riscv/mm/Makefile | 1 -
> drivers/misc/Makefile | 1 +
> {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> 3 files changed, 1 insertion(+), 1 deletion(-)
> rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
Why isn't this in drivers/edac/ ?
why is this a misc driver? Seems like it should sit next to the edac
stuff.
thanks,
greg k-h
