Quoting Paul Cercueil (2019-07-01 04:36:06) > The code was setting the bit 21 of the CPCCR register to use a divider > of 2 for the "pll half" clock, and clearing the bit to use a divider > of 1. > > This is the opposite of how this register field works: a cleared bit > means that the /2 divider is used, and a set bit means that the divider > is 1. > > Restore the correct behaviour using the newly introduced .div_table > field. > > Signed-off-by: Paul Cercueil <p...@crapouillou.net> > ---
Applied to clk-next. Does this need a fixes tag?
