On 08.08.2019 21:40, Andrew Lunn wrote: >> @@ -568,6 +568,11 @@ int phy_start_aneg(struct phy_device *phydev) >> if (err < 0) >> goto out_unlock; >> >> + /* The PHY may not yet have cleared aneg-completed and link-up bit >> + * w/o this delay when the following read is done. >> + */ >> + usleep_range(1000, 2000); >> + > > Hi Heiner > > Does 802.3 C22 say anything about this? > C22 says: "The Auto-Negotiation process shall be restarted by setting bit 0.9 to a logic one. This bit is self- clearing, and a PHY shall return a value of one in bit 0.9 until the Auto-Negotiation process has been initiated."
Maybe we should read bit 0.9 in genphy_update_link() after having read BMSR and report aneg-complete and link-up as false (no matter of their current value) if 0.9 is set. > If this PHY is broken with respect to the standard, i would prefer the > workaround is in the PHY specific driver code, not generic core code. > Based on the C22 statement above the PHY may not be broken and the typical time between two MDIO accesses is sufficient for the PHY to clear the bits. I think of MDIO bus access functions in network chips that have a 10us-20us delay after each MDIO access. On HNS3 this may not be the case. > Andrew > Heiner