> -----Original Message----- > From: Stephen Boyd <[email protected]> > Sent: 2019年8月14日 2:30 > To: Mark Rutland <[email protected]>; Michael Turquette > <[email protected]>; Rob Herring <[email protected]>; Shawn Guo > <[email protected]>; Wen He <[email protected]>; > [email protected]; [email protected]; > [email protected] > Cc: Leo Li <[email protected]>; [email protected]; Wen He > <[email protected]> > Subject: [EXT] Re: [v1 2/3] dt/bindings: clk: Add DT bindings for LS1028A > Display output interface > > Caution: EXT Email > > Quoting Wen He (2019-08-12 03:02:16) > > diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.txt > > b/Documentation/devicetree/bindings/clock/fsl,plldig.txt > > new file mode 100644 > > index 000000000000..29c5a6117809 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.txt > > @@ -0,0 +1,26 @@ > > +NXP QorIQ Layerscape LS1028A Display output interface Clock > > +=========================================================== > > Can you convert this to YAML?
Sure, no problem. > > > + > > +Required properties: > > + - compatible: shall contain "fsl,ls1028a-plldig" > > + - reg: Physical base address and size of the block registers > > + - #clock-cells: shall contain 1. > > As I said in the previous patch, this should probably be 0. Also, please order > this before the driver in the patch series and thread your messages please. If > you use git-send-email this is done for you pretty easily. Understand, Will prepare and send next version patch. Best Regards, Wen > > > + - clocks: a phandle + clock-specifier pairs, here should be > > + specify the reference clock of the system > > + > > +
