Hi Bjorn, Thanks a lot for your comments!
> -----Original Message----- > From: Bjorn Helgaas [mailto:helg...@kernel.org] > Sent: 2019年8月20日 3:20 > To: Z.q. Hou <zhiqiang....@nxp.com> > Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; gustavo.pimen...@synopsys.com; > jingooh...@gmail.com; robh...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; Leo Li <leoyang...@nxp.com>; > lorenzo.pieral...@arm.com; M.h. Lian <minghuan.l...@nxp.com> > Subject: Re: [PATCH 1/4] dt-bingings: PCI: Remove the num-lanes from > Required properties > > In subject: > > s/dt-bingings/dt-bindings/ > > Also, possibly > > s/PCI:/PCI: designware:/ > I'll fix them in v2. Thanks, Zhiqiang > since this only applies to designware-pcie.txt. > > On Mon, Aug 12, 2019 at 04:22:16AM +0000, Z.q. Hou wrote: > > From: Hou Zhiqiang <zhiqiang....@nxp.com> > > > > The num-lanes is not a mandatory property, e.g. on FSL Layerscape > > SoCs, the PCIe link training is completed automatically base on the > > selected SerDes protocol, it doesn't need the num-lanes to set-up the > > link width. > > > > It has been added in the Optional properties. This patch is to remove > > it from the Required properties. > > > > Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com> > > --- > > Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 - > > 1 file changed, 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt > > b/Documentation/devicetree/bindings/pci/designware-pcie.txt > > index 5561a1c060d0..bd880df39a79 100644 > > --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt > > +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt > > @@ -11,7 +11,6 @@ Required properties: > > the ATU address space. > > (The old way of getting the configuration address space from "ranges" > > is deprecated and should be avoided.) > > -- num-lanes: number of lanes to use > > RC mode: > > - #address-cells: set to <3> > > - #size-cells: set to <2> > > -- > > 2.17.1 > >
