On Mon, Aug 05, 2019 at 03:39:08PM +0100, Hanna Hawa wrote: > Document Amazon's Annapurna Labs L1 EDAC SoC binding. > > Signed-off-by: Hanna Hawa <hhh...@amazon.com> > --- > .../devicetree/bindings/edac/amazon,al-l1-edac.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt > > diff --git a/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt > b/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt > new file mode 100644 > index 000000000000..2ae8370216bc > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt > @@ -0,0 +1,14 @@ > +* Amazon's Annapurna Labs L1 EDAC > + > +Amazon's Annapurna Labs SoCs supports L1 single bit correction and > +two bits detection capability based on ARM implementation. > + > +Required properties: > +- compatible: > + should be "amazon,al-l1-edac".
Why is this even in DT? AFAICT, this is all just CortexA57 core features (i.e. nothing Amazon specific). The core type and the ECC capabilities are discoverable. Rob
