Le 20/08/2019 à 06:36, Alastair D'Silva a écrit :
On Fri, 2019-08-16 at 15:52 +0000, Christophe Leroy wrote:
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Thanks Christophe, I'm trying a somewhat different approach that requires less knowledge of assembler. Handling of CPU_FTR_COHERENT_ICACHE is outside this function. The code below is not a patch as my tree is a bit messy, sorry:
Can we be 100% sure that GCC won't add any code accessing some global data or stack while the Data MMU is OFF ?
Christophe
/** * flush_dcache_icache_phys() - Flush a page by it's physical address * @addr: the physical address of the page */ static void flush_dcache_icache_phys(unsigned long addr) { register unsigned long msr; register unsigned long dlines = PAGE_SIZE >> l1_dcache_shift(); register unsigned long dbytes = l1_dcache_bytes(); register unsigned long ilines = PAGE_SIZE >> l1_icache_shift(); register unsigned long ibytes = l1_icache_bytes(); register unsigned long i; register unsigned long address = addr; /* * Clear the DR bit so that we operate on physical * rather than virtual addresses */ msr = mfmsr(); mtmsr(msr & ~(MSR_DR)); /* Write out the data cache */ for (i = 0; i < dlines; i++, address += dbytes) dcbst((void *)address); /* Invalidate the instruction cache */ address = addr; for (i = 0; i < ilines; i++, address += ibytes) icbi((void *)address); mtmsr(msr); } void test_flush_phys(unsigned long addr) { flush_dcache_icache_phys(addr); } This gives the following assembler (using pmac32_defconfig): 000003cc <test_flush_phys>: 3cc: 94 21 ff f0 stwu r1,-16(r1) 3d0: 7d 00 00 a6 mfmsr r8 3d4: 55 09 07 34 rlwinm r9,r8,0,28,26 3d8: 7d 20 01 24 mtmsr r9 3dc: 39 20 00 80 li r9,128 3e0: 7d 29 03 a6 mtctr r9 3e4: 39 43 10 00 addi r10,r3,4096 3e8: 7c 69 1b 78 mr r9,r3 3ec: 7c 00 48 6c dcbst 0,r9 3f0: 39 29 00 20 addi r9,r9,32 3f4: 42 00 ff f8 bdnz 3ec <test_flush_phys+0x20> 3f8: 7c 00 1f ac icbi 0,r3 3fc: 38 63 00 20 addi r3,r3,32 400: 7f 8a 18 40 cmplw cr7,r10,r3 404: 40 9e ff f4 bne cr7,3f8 <test_flush_phys+0x2c> 408: 7d 00 01 24 mtmsr r8 40c: 38 21 00 10 addi r1,r1,16 410: 4e 80 00 20 blr