From: Kan Liang <[email protected]> The slots event supports sampling. Users may sampling read slots and metrics events, e.g perf record -e '{slots, topdown-retiring}:S'. But the metrics event will reset the fixed counter 3 which will impact the sampling of the slots event.
Add specific validate_group() support to reject the case and error out for Icelake. An alternative fix may unconditionally disable SLOTS sampling. But it's not a decent fix. Because users may want to only sampling slot events without topdown metrics event. Signed-off-by: Kan Liang <[email protected]> --- arch/x86/events/core.c | 4 ++++ arch/x86/events/intel/core.c | 20 ++++++++++++++++++++ arch/x86/events/perf_event.h | 2 ++ 3 files changed, 26 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 77573fa379dc..7fb98890d885 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2057,7 +2057,11 @@ static int validate_group(struct perf_event *event) fake_cpuc->n_events = 0; ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); + if (ret) + goto out; + if (x86_pmu.validate_group) + ret = x86_pmu.validate_group(fake_cpuc, n); out: free_fake_cpuc(fake_cpuc); return ret; diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 7925cf8830eb..4e0d60fcd1eb 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4489,6 +4489,25 @@ static __init void intel_ht_bug(void) x86_pmu.stop_scheduling = intel_stop_scheduling; } +static int icl_validate_group(struct cpu_hw_events *cpuc, int n) +{ + bool has_sampling_slots = false, has_metrics = false; + struct perf_event *e; + int i; + + for (i = 0; i < n; i++) { + e = cpuc->event_list[i]; + if (is_slots_event(e) && is_sampling_event(e)) + has_sampling_slots = true; + + if (is_metric_event(e)) + has_metrics = true; + } + if (unlikely(has_sampling_slots && has_metrics)) + return -EINVAL; + return 0; +} + EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") @@ -5334,6 +5353,7 @@ __init int intel_pmu_init(void) intel_pmu_pebs_data_source_skl(pmem); x86_pmu.update_topdown_event = icl_update_topdown_event; x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; + x86_pmu.validate_group = icl_validate_group; pr_cont("Icelake events, "); name = "icelake"; break; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 7c59f08fadc0..34c6ab5cafe8 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -629,6 +629,8 @@ struct x86_pmu { int perfctr_second_write; u64 (*limit_period)(struct perf_event *event, u64 l); + int (*validate_group)(struct cpu_hw_events *cpuc, int n); + /* PMI handler bits */ unsigned int late_ack :1, counter_freezing :1; -- 2.17.1
