[RFC v1 8/9] KVM: X86: MSR_IA32_PERF_CAPABILITIES MSR emulation

[Luwei Kang]

Expose some bits of definition which relate with enable
PEBS to KVM guest especially PEBS via PT feature.

Signed-off-by: Luwei Kang <luwei.k...@intel.com>
---
 arch/x86/include/asm/kvm_host.h  |  1 +
 arch/x86/include/asm/msr-index.h |  3 +++
 arch/x86/kvm/vmx/vmx.c           | 14 ++++++++++++++
 3 files changed, 18 insertions(+)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 2d9b0f9..94af338 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -576,6 +576,7 @@ struct kvm_vcpu_arch {
        u64 ia32_xss;
        u64 microcode_version;
        u64 arch_capabilities;
+       u64 ia32_perf_capabilities;
 
        /*
         * Paging state of the vcpu
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6321acb..4932dec 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -137,6 +137,9 @@
 #define MSR_IA32_PEBS_ENABLE           0x000003f1
 #define MSR_PEBS_DATA_CFG              0x000003f2
 #define MSR_IA32_DS_AREA               0x00000600
+#define MSR_IA32_PERF_CAP_PEBS_TRAP    (1UL << 6)
+#define MSR_IA32_PERF_CAP_PEBS_ARCH_REG        (1UL << 7)
+#define MSR_IA32_PERF_CAP_PEBS_REC_FMT (0xfUL << 8)
 #define MSR_IA32_PERF_CAP_PEBS_OUTPUT_PT       (1UL << 16)
 #define MSR_IA32_PERF_CAPABILITIES     0x00000345
 #define MSR_PEBS_LD_LAT_THRESHOLD      0x000003f6
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index dbff8f0..71e3d42 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1737,6 +1737,16 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct 
msr_data *msr_info)
                        return 1;
                msr_info->data = vcpu->arch.ia32_xss;
                break;
+       case MSR_IA32_PERF_CAPABILITIES:
+               if (!vmx_pdcm_supported() || !vmx_pebs_supported())
+                       return 1;
+               rdmsrl(MSR_IA32_PERF_CAPABILITIES, msr_info->data);
+               msr_info->data = msr_info->data &
+                       (MSR_IA32_PERF_CAP_PEBS_TRAP |
+                        MSR_IA32_PERF_CAP_PEBS_ARCH_REG |
+                        MSR_IA32_PERF_CAP_PEBS_REC_FMT |
+                        MSR_IA32_PERF_CAP_PEBS_OUTPUT_PT);
+               break;
        case MSR_IA32_RTIT_CTL:
                if (pt_mode != PT_MODE_HOST_GUEST)
                        return 1;
@@ -1981,6 +1991,10 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct 
msr_data *msr_info)
                else
                        clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
                break;
+       case MSR_IA32_PERF_CAPABILITIES:
+               if (!vmx_pdcm_supported() || !vmx_pebs_supported())
+                       return 1;
+               break;
        case MSR_IA32_RTIT_CTL:
                if ((pt_mode != PT_MODE_HOST_GUEST) ||
                        vmx_rtit_ctl_check(vcpu, data) ||
-- 
1.8.3.1