mt25qu512a is rebranded after its spinoff from STM, so it is different only in term of operating frequency, JEDEC id is same as that of n25q512a. SPI_NOR_4B_OPCODES is appended to flash property. This flash is tested for Single I/O and QUAD I/O mode on LS1046FRWY.
Signed-off-by: Kuldeep Singh <[email protected]> Signed-off-by: Ashish Kumar <[email protected]> Reviewed-by: Vignesh Raghavendra <[email protected]> --- v4: -Reword commit message as per review comments from tudor. - split into seperate patch v3: -Reword commits msg -rebase to top of mtd-linux spi-nor/next v2: Incorporate review comments from Vignesh drivers/mtd/spi-nor/spi-nor.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 73172d7f512b..b585f3fee4f0 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1876,7 +1876,18 @@ static const struct flash_info spi_nor_ids[] = { { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + + /* Micron */ + /* n25q512a is rebraned as mt25qu512a after spin-off from ST, + * JEDEC id remains same. + * Operational frequency and Read Performance has increased + */ + { + "mt25qu512a(n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024, + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) + }, + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, -- 2.17.1
