> On Sep 3, 2019, at 8:17 AM, Dave Hansen <dave.han...@intel.com> wrote: > > On 8/23/19 3:52 PM, Nadav Amit wrote: >> n_pages concurrent +deferred-pti change >> ------- ---------- ------------- ------ >> 1 2119 1986 -6.7% >> 10 6791 5417 -20% >> >> Please let me know if I missed something that affects security or >> performance. > > Hi Nadav, > > Is this in a VM or on bare metal? Could you also share the bare > /proc/cpuinfo for one of the CPU threads? I want to make sure that any > oddities in the stepping or microcode are known.
Bare-metal. Note that some of the benefit does come from having tighter loops for INVPCID/INVLPG, but the big difference is due to INVPCID being slower. I am kind of surprised that you are surprised. I was under the impression that INVPCID-single lower performance is known. Let me know if I did something wrong. processor : 55 vendor_id : GenuineIntel cpu family : 6 model : 79 model name : Intel(R) Xeon(R) CPU E5-2660 v4 @ 2.00GHz stepping : 1 microcode : 0xb000036 cpu MHz : 2403.035 cache size : 35840 KB physical id : 1 siblings : 28 core id : 14 cpu cores : 14 apicid : 61 initial apicid : 61 fpu : yes fpu_exception : yes cpuid level : 20 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdt_a rdseed adx smap intel_pt xsaveopt cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts md_clear flush_l1d bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs bogomips : 4001.56 clflush size : 64 cache_alignment : 64 address sizes : 46 bits physical, 48 bits virtual power management:
