On Mon, Sep 16, 2019 at 02:50:17PM +0200, Neil Armstrong wrote: > Add PCIE bindings for the Amlogic G12A SoC, the support is the same > but the PHY is shared with USB3 to control the differential lines. > > Thus this adds a phy phandle to control the PHY, and only requires the > MIPI clock for the Amlogic AXG SoC Family. > > Signed-off-by: Neil Armstrong <narmstr...@baylibre.com> > Reviewed-by: Rob Herring <r...@kernel.org> > ---
Reviewed-by: Andrew Murray <andrew.mur...@arm.com> > .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > index efa2c8b9b85a..84fdc422792e 100644 > --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > @@ -9,13 +9,16 @@ Additional properties are described here: > > Required properties: > - compatible: > - should contain "amlogic,axg-pcie" to identify the core. > + should contain : > + - "amlogic,axg-pcie" for AXG SoC Family > + - "amlogic,g12a-pcie" for G12A SoC Family > + to identify the core. > - reg: > should contain the configuration address space. > - reg-names: Must be > - "elbi" External local bus interface registers > - "cfg" Meson specific registers > - - "phy" Meson PCIE PHY registers > + - "phy" Meson PCIE PHY registers for AXG SoC Family > - "config" PCIe configuration space > - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. > - clocks: Must contain an entry for each entry in clock-names. > @@ -23,12 +26,13 @@ Required properties: > - "pclk" PCIe GEN 100M PLL clock > - "port" PCIe_x(A or B) RC clock gate > - "general" PCIe Phy clock > - - "mipi" PCIe_x(A or B) 100M ref clock gate > + - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family > - resets: phandle to the reset lines. > - reset-names: must contain "phy" "port" and "apb" > - - "phy" Share PHY reset > + - "phy" Share PHY reset for AXG SoC Family > - "port" Port A or B reset > - "apb" Share APB reset > +- phys: should contain a phandle to the shared phy for G12A SoC Family > - device_type: > should be "pci". As specified in designware-pcie.txt > > -- > 2.22.0 >
