Hi Piotr, I love your patch! Yet something to improve:
[auto build test ERROR on linus/master] [cannot apply to v5.3 next-20190915] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Piotr-Sroka/mtd-rawnand-Add-Cadence-NAND-controller-driver/20190916-205004 config: parisc-allyesconfig (attached as .config) compiler: hppa-linux-gcc (GCC) 7.4.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=7.4.0 make.cross ARCH=parisc If you fix the issue, kindly add following tag Reported-by: kbuild test robot <l...@intel.com> All errors (new ones prefixed by >>): drivers/mtd/nand/raw/cadence-nand-controller.c: In function 'cadence_nand_read_buf': >> drivers/mtd/nand/raw/cadence-nand-controller.c:1877:3: error: implicit >> declaration of function 'readsl'; did you mean 'readl'? >> [-Werror=implicit-function-declaration] readsl(cdns_ctrl->io.virt, buf, len_in_words); ^~~~~~ readl drivers/mtd/nand/raw/cadence-nand-controller.c: In function 'cadence_nand_write_buf': >> drivers/mtd/nand/raw/cadence-nand-controller.c:1930:3: error: implicit >> declaration of function 'writesl'; did you mean 'writel'? >> [-Werror=implicit-function-declaration] writesl(cdns_ctrl->io.virt, buf, len_in_words); ^~~~~~~ writel cc1: some warnings being treated as errors vim +1877 drivers/mtd/nand/raw/cadence-nand-controller.c 1860 1861 static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl, 1862 u8 *buf, int len) 1863 { 1864 u8 thread_nr = 0; 1865 u32 sdma_size; 1866 int status; 1867 1868 /* Wait until slave DMA interface is ready to data transfer. */ 1869 status = cadence_nand_wait_on_sdma(cdns_ctrl, &thread_nr, &sdma_size); 1870 if (status) 1871 return status; 1872 1873 if (!cdns_ctrl->caps1->has_dma) { 1874 int len_in_words = len >> 2; 1875 1876 /* read alingment data */ > 1877 readsl(cdns_ctrl->io.virt, buf, len_in_words); 1878 if (sdma_size > len) { 1879 /* read rest data from slave DMA interface if any */ 1880 readsl(cdns_ctrl->io.virt, cdns_ctrl->buf, 1881 sdma_size / 4 - len_in_words); 1882 /* copy rest of data */ 1883 memcpy(buf + (len_in_words << 2), cdns_ctrl->buf, 1884 len - (len_in_words << 2)); 1885 } 1886 return 0; 1887 } 1888 1889 if (cdns_ctrl->dmac && cadence_nand_dma_buf_ok(cdns_ctrl, buf, len)) { 1890 status = cadence_nand_slave_dma_transfer(cdns_ctrl, buf, 1891 cdns_ctrl->io.dma, 1892 len, DMA_FROM_DEVICE); 1893 if (status == 0) 1894 return 0; 1895 1896 dev_warn(cdns_ctrl->dev, 1897 "Slave DMA transfer failed. Try again using bounce buffer."); 1898 } 1899 1900 /* If DMA transfer is not possible or failed then use bounce buffer. */ 1901 status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf, 1902 cdns_ctrl->io.dma, 1903 sdma_size, DMA_FROM_DEVICE); 1904 1905 if (status) { 1906 dev_err(cdns_ctrl->dev, "Slave DMA transfer failed"); 1907 return status; 1908 } 1909 1910 memcpy(buf, cdns_ctrl->buf, len); 1911 1912 return 0; 1913 } 1914 1915 static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl, 1916 const u8 *buf, int len) 1917 { 1918 u8 thread_nr = 0; 1919 u32 sdma_size; 1920 int status; 1921 1922 /* Wait until slave DMA interface is ready to data transfer. */ 1923 status = cadence_nand_wait_on_sdma(cdns_ctrl, &thread_nr, &sdma_size); 1924 if (status) 1925 return status; 1926 1927 if (!cdns_ctrl->caps1->has_dma) { 1928 int len_in_words = len >> 2; 1929 > 1930 writesl(cdns_ctrl->io.virt, buf, len_in_words); 1931 if (sdma_size > len) { 1932 /* copy rest of data */ 1933 memcpy(cdns_ctrl->buf, buf + (len_in_words << 2), 1934 len - (len_in_words << 2)); 1935 /* write all expected by nand controller data */ 1936 writesl(cdns_ctrl->io.virt, cdns_ctrl->buf, 1937 sdma_size / 4 - len_in_words); 1938 } 1939 1940 return 0; 1941 } 1942 1943 if (cdns_ctrl->dmac && cadence_nand_dma_buf_ok(cdns_ctrl, buf, len)) { 1944 status = cadence_nand_slave_dma_transfer(cdns_ctrl, (void *)buf, 1945 cdns_ctrl->io.dma, 1946 len, DMA_TO_DEVICE); 1947 if (status == 0) 1948 return 0; 1949 1950 dev_warn(cdns_ctrl->dev, 1951 "Slave DMA transfer failed. Try again using bounce buffer."); 1952 } 1953 1954 /* If DMA transfer is not possible or failed then use bounce buffer. */ 1955 memcpy(cdns_ctrl->buf, buf, len); 1956 1957 status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf, 1958 cdns_ctrl->io.dma, 1959 sdma_size, DMA_TO_DEVICE); 1960 1961 if (status) 1962 dev_err(cdns_ctrl->dev, "Slave DMA transfer failed"); 1963 1964 return status; 1965 } 1966 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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