Quoting Peng Fan (2019-09-08 20:39:34) > From: Peng Fan <[email protected]> > > According to PLL1443XA and PLL1416X spec, > "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to > output unstable clock until lock time passes. PLL1416X/PLL1443XA may > generate a glitch at FOUT." > > So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch. > In the end of set rate, BYPASS will be cleared. > > When prepare clock, also need to take care to avoid glitch. So > we also follow Spec to set BYPASS before RESETB changed from 0 to 1. > And add a check if the RESETB is already 0, directly return 0; > > Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") > Reviewed-by: Leonard Crestez <[email protected]> > Signed-off-by: Peng Fan <[email protected]> > ---
Applied to clk-next
