Update DT node name clock-controller to clock-display, also change the property #clock-cells value to zero.
This update according the feedback of the Display output interface clock driver upstream. Link: https://lore.kernel.org/patchwork/patch/1113832/ Signed-off-by: Wen He <[email protected]> --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 51fa8f57fdac..db1e186352d8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -79,10 +79,10 @@ clock-output-names = "phy_27m"; }; - dpclk: clock-controller@f1f0000 { + dpclk: clock-display@f1f0000 { compatible = "fsl,ls1028a-plldig"; reg = <0x0 0xf1f0000 0x0 0xffff>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&osc_27m>; }; @@ -665,7 +665,7 @@ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, <0 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "DE", "SE"; - clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>, + clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, <&clockgen 2 2>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; -- 2.17.1
