On 23. 09. 19 16:36, Valentin Schneider wrote: > Since the enabling and disabling of IRQs within preempt_schedule_irq() > is contained in a need_resched() loop, we don't need the outer arch > code loop. > > Signed-off-by: Valentin Schneider <[email protected]> > Cc: Michal Simek <[email protected]> > --- > arch/microblaze/kernel/entry.S | 5 ----- > 1 file changed, 5 deletions(-) > > diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S > index 4e1b567becd6..de7083bd1d24 100644 > --- a/arch/microblaze/kernel/entry.S > +++ b/arch/microblaze/kernel/entry.S > @@ -738,14 +738,9 @@ no_intr_resched: > andi r5, r5, _TIF_NEED_RESCHED; > beqi r5, restore /* if zero jump over */ > > -preempt: > /* interrupts are off that's why I am calling preempt_chedule_irq */ > bralid r15, preempt_schedule_irq > nop > - lwi r11, CURRENT_TASK, TS_THREAD_INFO; /* get thread info */ > - lwi r5, r11, TI_FLAGS; /* get flags in thread info */ > - andi r5, r5, _TIF_NEED_RESCHED; > - bnei r5, preempt /* if non zero jump to resched */ > restore: > #endif > VM_OFF /* MS: turn off MMU */ >
Looks reasonable and also tested on HW. I expect you want me to take it via microblaze tree that's why applied. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
