> -----Original Message----- > From: Vinod Koul <[email protected]> > Sent: Thursday, September 26, 2019 10:51 PM > To: Radhey Shyam Pandey <[email protected]> > Cc: [email protected]; Michal Simek <[email protected]>; > [email protected]; [email protected]; Appana Durga > Kedareswara Rao <[email protected]>; [email protected]; > [email protected]; [email protected] > Subject: Re: [PATCH -next 7/8] dmaengine: xilinx_dma: Check for both idle > and halted state in axidma stop_transfer > > On 05-09-19, 22:07, Radhey Shyam Pandey wrote: > > From: Nicholas Graumann <[email protected]> > > > > When polling for a stopped transfer in AXI DMA mode, in some cases the > > status of the channel may indicate IDLE instead of HALTED if the > > channel was reset due to an error. > > > > Signed-off-by: Nicholas Graumann <[email protected]> > > Signed-off-by: Radhey Shyam Pandey > <[email protected]> > > --- > > drivers/dma/xilinx/xilinx_dma.c | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c > b/drivers/dma/xilinx/xilinx_dma.c > > index b5dd62a..0896e07 100644 > > --- a/drivers/dma/xilinx/xilinx_dma.c > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > @@ -1092,8 +1092,9 @@ static int xilinx_dma_stop_transfer(struct > xilinx_dma_chan *chan) > > > > /* Wait for the hardware to halt */ > > return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, > val, > > - val & XILINX_DMA_DMASR_HALTED, 0, > > - XILINX_DMA_LOOP_COUNT); > > + val | (XILINX_DMA_DMASR_IDLE | > > + XILINX_DMA_DMASR_HALTED), > > The condition was bitwise AND and now is OR.. ??
Ah, it should be same as before . Only _IDLE mask should be in OR. Also on second thought to this patch- we need to describe which error scenario "in some cases the status of the channel may indicate IDLE instead of HALTED" as mentioned in commit description. @Nick: Can you comment? > > > + 0, XILINX_DMA_LOOP_COUNT); > > } > > > > /** > > -- > > 2.7.4 > > -- > ~Vinod
