> On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela
> <gayatri.kamm...@intel.com> wrote:
>
> Thank you for the series, I'll comment them later.
Thank you Andy!
>
> For now, check how to properly setup prefix for all patches. The Title all
> broken.
I'm sorry about that. I will fix it in v2
>
> > Patch 1: Cleans up termination lines
> > Patch 2: Refactor driver for ease of adding new SoCs Patch 3: Refactor
> > debugfs entry for PCH IPs power gating status Patch 4: Add Tiger Lake
> > legacy support to pmc_core Patch 5: Add Elkhart Lake legacy support to
> > pmc_core
> >
> > All the information regarding the PCH IPs and names of IPs will be
> > available in *future* Intel's Platform Controller Hub (PCH) External
> > Design Specification
> > (EDS) document.
>
> When?
I was told it will be available in the upcoming release of EDS document. I am
not aware of the timeline. I will update the timeline in v2.
