From: Will Deacon <will.dea...@arm.com>

commit 2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1 upstream.

While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.

We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.

Signed-off-by: Will Deacon <will.dea...@arm.com>
Signed-off-by: Niklas Cassel <niklas.cas...@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>

---
 arch/arm64/kernel/cpufeature.c |    5 +++++
 1 file changed, 5 insertions(+)

--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -838,6 +838,11 @@ static bool unmap_kernel_at_el0(const st
        switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
        case MIDR_CAVIUM_THUNDERX2:
        case MIDR_BRCM_VULCAN:
+       case MIDR_CORTEX_A53:
+       case MIDR_CORTEX_A55:
+       case MIDR_CORTEX_A57:
+       case MIDR_CORTEX_A72:
+       case MIDR_CORTEX_A73:
                return false;
        }
 


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