The following commit has been merged into the perf/urgent branch of tip: Commit-ID: b01a8e2edb924feee1b66f74df1198788fc37cca Gitweb: https://git.kernel.org/tip/b01a8e2edb924feee1b66f74df1198788fc37cca Author: Kan Liang <kan.li...@linux.intel.com> AuthorDate: Tue, 08 Oct 2019 08:50:09 -07:00 Committer: Ingo Molnar <mi...@kernel.org> CommitterDate: Wed, 09 Oct 2019 12:44:18 +02:00
perf/x86/msr: Add Tiger Lake CPU support Tiger Lake is the followon to Ice Lake. PPERF and SMI_COUNT MSRs are also supported. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware. Signed-off-by: Kan Liang <kan.li...@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <pet...@infradead.org> Cc: Linus Torvalds <torva...@linux-foundation.org> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Thomas Gleixner <t...@linutronix.de> Link: https://lkml.kernel.org/r/1570549810-25049-9-git-send-email-kan.li...@linux.intel.com Signed-off-by: Ingo Molnar <mi...@kernel.org> --- arch/x86/events/msr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 8515512..6f86650 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -95,6 +95,8 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ICELAKE: case INTEL_FAM6_ICELAKE_X: case INTEL_FAM6_ICELAKE_D: + case INTEL_FAM6_TIGERLAKE_L: + case INTEL_FAM6_TIGERLAKE: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break;
