> The only alternative is to assume a weak memory model, and add the required > barriers to spin_unlock -- something that has been explicitly avoided, but
We have the barriers in spin_unlock already for Pentium Pro and IDT Winchip systems. The Winchip explicitly supports out of order store (and was about 10-20% faster with it set this way), the PPro has some annoying little store ordering bugs which is why we xchgb out of spin_unlock in those cases. > The complaint that broken old ppros get more broken seems to be bogus as well: > wmb on i386 never catered to the old ppro to start with. The errata seem to There are only a couple of awkward cases with the PPro and we carefully work around them. The other half of the work is the flush_write_buffers. > Buggy ppros: I have no interest in, given the vague errata and apparently > unfixable problems with lockless code; anybody is welcome to try adding > whatever they like to help them work, but again please don't confuse that > with having anything to do with this patch... PPro was fixed, made to work and brutally tested on quad PPro. There are cases that wouldn't work (PPro + AGP which never happens) and there are cases that need specific handling (PPro + Voodoo card and some other 3D bits) which are handled currently in the X server. The rest is fine. > Winchip: can any of these CPUs with ooostores do SMP? If not, then smp_wmb > can also be a simple barrier on i386 too. The IDT Winchip can do SMP apparently. Nobody has ever seen an SMP winchip board so I don't think it matters and even if one existed we wouldn't support it anyway However - You've not shown the patch has any performance gain - You've probably broken Pentium Pro - and for modern processors its still not remotely clear your patch is correct because of NT stores. So NAK Alan - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/