On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <and...@aj.id.au> wrote: > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <and...@aj.id.au>
Reviewed-by: Joel Stanley <j...@jms.id.au>
