Errata: unsupported request error on inbound posted write
transaction, PCIe controller reports advisory error instead
of uncorrectable error message to RC.

Signed-off-by: Xiaowei Bao <xiaowei....@nxp.com>
---
v3: 
 - Use BIT replce the expression.

 drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13 +++++++++++++
 drivers/pci/controller/mobiveil/pcie-mobiveil.h           |  4 ++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c 
b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
index 56603ea..82bb38d 100644
--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
@@ -49,6 +49,19 @@ static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
        struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
        int win_idx;
        u8 bar;
+       u32 val;
+
+       /*
+        * Errata: unsupported request error on inbound posted write
+        * transaction, PCIe controller reports advisory error instead
+        * of uncorrectable error message to RC.
+        * workaround: set the bit20(unsupported_request_Error_severity) with
+        * value 1 in uncorrectable_Error_Severity_Register, make the
+        * unsupported request error generate the fatal error.
+        */
+       val =  csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
+       val |= BIT(UNSUPPORTED_REQUEST_ERROR_SHIFT);
+       csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
 
        ep->bar_num = PCIE_LX2_BAR_NUM;
 
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h 
b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 7308fa4..a40707e 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -123,6 +123,10 @@
 #define GPEX_BAR_SIZE_UDW              0x4DC
 #define GPEX_BAR_SELECT                        0x4E0
 
+#define CFG_UNCORRECTABLE_ERROR_SEVERITY       0x10c
+#define UNSUPPORTED_REQUEST_ERROR_SHIFT                20
+#define CFG_UNCORRECTABLE_ERROR_MASK           0x108
+
 /* starting offset of INTX bits in status register */
 #define PAB_INTX_START                 5
 
-- 
2.9.5

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