Convert LLCC bindings to DT schema format using json-schema.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ran...@codeaurora.org>
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --------------
.../bindings/arm/msm/qcom,llcc.yaml | 54 +++++++++++++++++++
2 files changed, 54 insertions(+), 41 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
deleted file mode 100644
index eaee06b2d8f2..000000000000
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-== Introduction==
-
-LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
-that can be shared by multiple clients. Clients here are different cores in the
-SOC, the idea is to minimize the local caches at the clients and migrate to
-common pool of memory. Cache memory is divided into partitions called slices
-which are assigned to clients. Clients can query the slice details, activate
-and deactivate them.
-
-Properties:
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be "qcom,sdm845-llcc"
-
-- reg:
- Usage: required
- Value Type: <prop-encoded-array>
- Definition: The first element specifies the llcc base start address and
- the size of the register region. The second element
specifies
- the llcc broadcast base address and size of the register
region.
-
-- reg-names:
- Usage: required
- Value Type: <stringlist>
- Definition: Register region names. Must be "llcc_base",
"llcc_broadcast_base".
-
-- interrupts:
- Usage: required
- Definition: The interrupt is associated with the llcc edac device.
- It's used for llcc cache single and double bit error
detection
- and reporting.
-
-Example:
-
- cache-controller@1100000 {
- compatible = "qcom,sdm845-llcc";
- reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
new file mode 100644
index 000000000000..5ac90d101807
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Last Level Cache Controller
+
+maintainers:
+ - Rishabh Bhatnagar <risha...@codeaurora.org>
+ - Sai Prakash Ranjan <saiprakash.ran...@codeaurora.org>
+
+description: |
+ LLCC (Last Level Cache Controller) provides last level of cache memory in
SoC,
+ that can be shared by multiple clients. Clients here are different cores in
the
+ SoC, the idea is to minimize the local caches at the clients and migrate to
+ common pool of memory. Cache memory is divided into partitions called slices
+ which are assigned to clients. Clients can query the slice details, activate
+ and deactivate them.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-llcc
+
+ reg:
+ items:
+ - description: LLCC base register region
+ - description: LLCC broadcast base register region
+
+ reg-names:
+ items:
+ - const: llcc_base
+ - const: llcc_broadcast_base
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
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