> -----Original Message-----
> From: Peng Ma <peng...@nxp.com>
> Sent: Sunday, October 20, 2019 9:22 PM
> To: vk...@kernel.org
> Cc: dan.j.willi...@intel.com; Leo Li <leoyang...@nxp.com>;
> k.kozlowsk...@gmail.com; Fabio Estevam <fabio.este...@nxp.com>;
> dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org; Peng Ma
> <peng...@nxp.com>
> Subject: [V2] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A
> platform
>
> Our platforms(such as LS1021A, LS1012A, LS1043A, LS1046A, LS1028A) with
> below
You only covered QorIQ SoCs, how about the situation for IMX SoCs?
> registers(CHCFG0 - CHCFG15) of eDMA as follows:
> *-----------------------------------------------------------*
> | Offset | OTHERS | LS1028A |
> |--------------|--------------------|-----------------------|
> | 0x0 | CHCFG0 | CHCFG3 |
> |--------------|--------------------|-----------------------|
> | 0x1 | CHCFG1 | CHCFG2 |
> |--------------|--------------------|-----------------------|
> | 0x2 | CHCFG2 | CHCFG1 |
> |--------------|--------------------|-----------------------|
> | 0x3 | CHCFG3 | CHCFG0 |
> |--------------|--------------------|-----------------------|
> | ... | ...... | ...... |
> |--------------|--------------------|-----------------------|
> | 0xC | CHCFG12 | CHCFG15 |
> |--------------|--------------------|-----------------------|
> | 0xD | CHCFG13 | CHCFG14 |
> |--------------|--------------------|-----------------------|
> | 0xE | CHCFG14 | CHCFG13 |
> |--------------|--------------------|-----------------------|
> | 0xF | CHCFG15 | CHCFG12 |
> *-----------------------------------------------------------*
>
> This patch is to improve edma driver to fit LS1028A platform.
>
> Signed-off-by: Peng Ma <peng...@nxp.com>
> ---
> Changed for V2:
> - Explaining what's the "Our platforms"
>
> drivers/dma/fsl-edma-common.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-
> common.c index b1a7ca9..611186b 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -7,6 +7,7 @@
> #include <linux/module.h>
> #include <linux/slab.h>
> #include <linux/dma-mapping.h>
> +#include <linux/sys_soc.h>
>
> #include "fsl-edma-common.h"
>
> @@ -42,6 +43,11 @@
>
> #define EDMA_TCD 0x1000
>
> +static struct soc_device_attribute soc_fixup_tuning[] = {
> + { .family = "QorIQ LS1028A"},
> + { },
> +};
> +
> static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) {
> struct edma_regs *regs = &fsl_chan->edma->regs; @@ -109,10
> +115,16 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
> u32 ch = fsl_chan->vchan.chan.chan_id;
> void __iomem *muxaddr;
> unsigned int chans_per_mux, ch_off;
> + int endian_diff[4] = {3, 1, -1, -3};
> u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs;
>
> chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr;
> ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
> +
> + if (!fsl_chan->edma->big_endian &&
> + soc_device_match(soc_fixup_tuning))
> + ch_off += endian_diff[ch_off % 4];
> +
This probably is not the best fix now. There is a new mux_configure32() API
added but it doesn't consider endianness. How about making it properly taken
care of endianness? And use it to set these registers?
> muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
> slot = EDMAMUX_CHCFG_SOURCE(slot);
>
> --
> 2.9.5
