On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote:
> The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power
> state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary
> power. On Windows ASPM L1 is enabled on the device and its upstream
> bridge, so it can make the Intel SoC reach PC8 or PC10 to save lots of
> power.
>
> In short, ASPM always gets disabled on bridge-to-bridge link.
Excelent finding :) I've heard several reports complaining that we can't
enter PC10 when TBT is enabled and I guess this explains it.
> The special case was part of first ASPM introduction patch, commit
> 7d715a6c1ae5 ("PCI: add PCI Express ASPM support"). However, it didn't
> explain why ASPM needs to be disabled in special bridge-to-bridge case.
>
> Let's remove the the special case, as PCIe spec already envisioned ASPM
> on bridge-to-bridge link.
>
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=207571
> Signed-off-by: Kai-Heng Feng <kai.heng.f...@canonical.com>
Reviewed-by: Mika Westerberg <mika.westerb...@linux.intel.com>
