Currently neither clocksource nor scheduler clock kernel framework support the clocks with variable frequency. Needless to say how many problems may cause the sudden base clocks frequency change. In a simplest case the system time will either slow down or speed up. Since on CM2.5 and earlier MIPS GIC timer is synchronously clocked with CPU we must set some limitations on using it for these frameworks if CPU frequency may change. First of all it's not safe to have the MIPS GIC used for scheduler timings. So we shouldn't proceed with the clocks registration in the sched-subsystem. Secondly we must significantly decrease the MIPS GIC clocksource rating. This will let the system to use it only as a last resort.
Note CM3.x-based systems may also experience the problems with MIPS GIC if the CPU-frequency change is activated for the whole CPU cluster instead of using the individual CPC core clocks divider. Signed-off-by: Serge Semin <[email protected]> Cc: Alexey Malahov <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Alessandro Zummo <[email protected]> Cc: Alexandre Belloni <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] --- drivers/clocksource/mips-gic-timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index 802b93fe3ae7..095d65b48920 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -185,7 +185,10 @@ static int __init __gic_clocksource_init(void) gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); /* Calculate a somewhat reasonable rating value. */ - gic_clocksource.rating = 200 + gic_frequency / 10000000; + if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) + gic_clocksource.rating = 200 + gic_frequency / 10000000; + else + gic_clocksource.rating = 99; ret = clocksource_register_hz(&gic_clocksource, gic_frequency); if (ret < 0) @@ -239,9 +242,11 @@ static int __init gic_clocksource_of_init(struct device_node *node) /* And finally start the counter */ clear_gic_config(GIC_CONFIG_COUNTSTOP); - sched_clock_register(mips_cm_is64 ? - gic_read_count_64 : gic_read_count_2x32, - 64, gic_frequency); + if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) { + sched_clock_register(mips_cm_is64 ? + gic_read_count_64 : gic_read_count_2x32, + 64, gic_frequency); + } return 0; } -- 2.25.1
