[PATCH 4.4 207/312] clk: xgene: Dont call __pa on ioremaped address

[Greg Kroah-Hartman]

From: Laura Abbott <labb...@redhat.com>

commit 06b113e9f28f8657715919087a3f54b77d1634ed upstream.

ioremaped addresses are not linearly mapped so the physical
address can not be figured out via __pa. More generally, there
is no guarantee that backing value of an ioremapped address
is a physical address at all. The value here is only used
for debugging so just drop the call to __pa on the ioremapped
address.

Fixes: 6ae5fd381251 ("clk: xgene: Silence sparse warnings")
Signed-off-by: Laura Abbott <labb...@redhat.com>
Acked-by: Loc Ho <l...@apm.com>
Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>

---
 drivers/clk/clk-xgene.c |   10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -218,22 +218,20 @@ static int xgene_clk_enable(struct clk_h
        struct xgene_clk *pclk = to_xgene_clk(hw);
        unsigned long flags = 0;
        u32 data;
-       phys_addr_t reg;
 
        if (pclk->lock)
                spin_lock_irqsave(pclk->lock, flags);
 
        if (pclk->param.csr_reg != NULL) {
                pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
-               reg = __pa(pclk->param.csr_reg);
                /* First enable the clock */
                data = xgene_clk_read(pclk->param.csr_reg +
                                        pclk->param.reg_clk_offset);
                data |= pclk->param.reg_clk_mask;
                xgene_clk_write(data, pclk->param.csr_reg +
                                        pclk->param.reg_clk_offset);
-               pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X 
value 0x%08X\n",
-                       clk_hw_get_name(hw), &reg,
+               pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n",
+                       clk_hw_get_name(hw),
                        pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
                        data);
 
@@ -243,8 +241,8 @@ static int xgene_clk_enable(struct clk_h
                data &= ~pclk->param.reg_csr_mask;
                xgene_clk_write(data, pclk->param.csr_reg +
                                        pclk->param.reg_csr_offset);
-               pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 
0x%08X value 0x%08X\n",
-                       clk_hw_get_name(hw), &reg,
+               pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n",
+                       clk_hw_get_name(hw),
                        pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
                        data);
        }