> -----Original Message-----
> From: Reinette Chatre <reinette.cha...@intel.com>
> Sent: Wednesday, May 6, 2020 6:50 PM
> To: t...@linutronix.de; fenghua...@intel.com; b...@alien8.de;
> tony.l...@intel.com
> Cc: kuo-lang.ts...@intel.com; ravi.v.shan...@intel.com; mi...@redhat.com;
> Moger, Babu <babu.mo...@amd.com>; h...@zytor.com; x...@kernel.org;
> linux-kernel@vger.kernel.org; Reinette Chatre <reinette.cha...@intel.com>
> Subject: [PATCH V3 2/4] x86/resctrl: Enumerate per-thread MBA
>
> From: Fenghua Yu <fenghua...@intel.com>
>
> Some systems support per-thread Memory Bandwidth Allocation (MBA) which
> applies a throttling delay value to each hardware thread instead of to
> a core. Per-thread MBA is enumerated by CPUID.
>
> No feature flag is shown in /proc/cpuinfo. User applications need to
> check a resctrl throttling mode info file to know if the feature is
> supported.
>
> Signed-off-by: Fenghua Yu <fenghua...@intel.com>
> Signed-off-by: Reinette Chatre <reinette.cha...@intel.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/kernel/cpu/cpuid-deps.c | 1 +
> arch/x86/kernel/cpu/scattered.c | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> index db189945e9b0..d0ec26ce7f66 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -286,6 +286,7 @@
> #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user
> entry SWAPGS path */
> #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* ""
> LFENCE in kernel entry SWAPGS path */
> #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock
> */
> +#define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread
> Memory Bandwidth Allocation */
>
> /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512
> BFLOAT16 instructions */
> diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-
> deps.c
> index 3cbe24ca80ab..3e30b26c50ef 100644
> --- a/arch/x86/kernel/cpu/cpuid-deps.c
> +++ b/arch/x86/kernel/cpu/cpuid-deps.c
> @@ -69,6 +69,7 @@ static const struct cpuid_dep cpuid_deps[] = {
> { X86_FEATURE_CQM_MBM_TOTAL,
> X86_FEATURE_CQM_LLC },
> { X86_FEATURE_CQM_MBM_LOCAL,
> X86_FEATURE_CQM_LLC },
> { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL },
> + { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA
> },
> {}
> };
>
> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> index 62b137c3c97a..bccfc9ff3cc1 100644
> --- a/arch/x86/kernel/cpu/scattered.c
> +++ b/arch/x86/kernel/cpu/scattered.c
> @@ -35,6 +35,7 @@ static const struct cpuid_bit cpuid_bits[] = {
> { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1
> },
> { X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2
> },
> { X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
> + { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3
> },
This is a CPUID feature. You can actually detect this feature without
checking vendor model in patch @1. This patch looks good to me.
> { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
> { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
> { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
> --
> 2.21.0
