This patch enables AMD Fam17h RAPL support for the Package level metric.
The support is as per AMD Fam17h Model31h (Zen2) and model 00-ffh (Zen1) PPR.

The same output is available via the energy-pkg pseudo event:

$ perf stat -a -I 1000 --per-socket -e power/energy-pkg/

Signed-off-by: Stephane Eranian <eran...@google.com>
---
 arch/x86/events/probe.c          |  4 ++++
 arch/x86/events/rapl.c           | 17 +++++++++++++++++
 arch/x86/include/asm/msr-index.h |  3 +++
 3 files changed, 24 insertions(+)

diff --git a/arch/x86/events/probe.c b/arch/x86/events/probe.c
index c2ede2f3b2770..b3a9df2e48dfa 100644
--- a/arch/x86/events/probe.c
+++ b/arch/x86/events/probe.c
@@ -26,6 +26,10 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, 
void *data)
 
                        grp->is_visible = not_visible;
 
+                       /* avoid unpopulated entries */
+                       if (!msr[bit].msr)
+                               continue;
+
                        if (msr[bit].test && !msr[bit].test(bit, data))
                                continue;
                        /* Virt sucks; you cannot tell if a R/O MSR is present 
:/ */
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index e98f627a13fa8..47ff20dfde889 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -526,6 +526,15 @@ static struct perf_msr intel_rapl_msrs[] = {
        [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, 
&rapl_events_psys_group,  test_msr },
 };
 
+static struct perf_msr amd_rapl_msrs[] = {
+       [PERF_RAPL_PP0]  = { 0, &rapl_events_cores_group, NULL},
+       [PERF_RAPL_PKG]  = { MSR_AMD_PKG_ENERGY_STATUS,  
&rapl_events_pkg_group,   test_msr },
+       [PERF_RAPL_RAM]  = { 0, &rapl_events_ram_group,   NULL},
+       [PERF_RAPL_PP1]  = { 0, &rapl_events_gpu_group,   NULL},
+       [PERF_RAPL_PSYS] = { 0, &rapl_events_psys_group,  NULL},
+};
+
+
 static int rapl_cpu_offline(unsigned int cpu)
 {
        struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu);
@@ -729,6 +738,13 @@ static struct rapl_model model_skl = {
        .rapl_msrs      = intel_rapl_msrs,
 };
 
+static struct rapl_model model_amd_fam17h = {
+       .events         = BIT(PERF_RAPL_PKG),
+       .apply_quirk    = false,
+       .msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
+       .rapl_msrs      = amd_rapl_msrs,
+};
+
 static const struct x86_cpu_id rapl_model_match[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,         &model_snb),
        X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,       &model_snbep),
@@ -757,6 +773,7 @@ static const struct x86_cpu_id rapl_model_match[] 
__initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,             &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,         &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,           &model_skl),
+       X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h),
        {},
 };
 MODULE_DEVICE_TABLE(x86cpu, rapl_model_match);
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 12c9684d59ba6..ef452b817f44f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -301,6 +301,9 @@
 #define MSR_PP1_ENERGY_STATUS          0x00000641
 #define MSR_PP1_POLICY                 0x00000642
 
+#define MSR_AMD_PKG_ENERGY_STATUS      0xc001029b
+#define MSR_AMD_RAPL_POWER_UNIT                0xc0010299
+
 /* Config TDP MSRs */
 #define MSR_CONFIG_TDP_NOMINAL         0x00000648
 #define MSR_CONFIG_TDP_LEVEL_1         0x00000649
-- 
2.26.2.761.g0e0b3e54be-goog

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