On Thu, Apr 23, 2020 at 09:56:54PM +0800, Zhenyu Ye wrote: > From: "Peter Zijlstra (Intel)" <[email protected]> > > tlb_flush_{pte|pmd|pud|p4d}_range() adjust the tlb->start and > tlb->end, then set corresponding cleared_*. > > Signed-off-by: Peter Zijlstra (Intel) <[email protected]> > Signed-off-by: Zhenyu Ye <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
