On Mon, Jun 01, 2020 at 10:50:36AM +0530, Sandipan Patra wrote: > Added support for dynamic clock freq configuration in pwm kernel driver. > Earlier the pwm driver used to cache boot time clock rate by pwm clock > parent during probe. Hence dynamically changing pwm frequency was not > possible for all the possible ranges. With this change, dynamic calculation > is enabled and it is able to set the requested period from sysfs knob > provided the value is supported by clock source. > > Changes mainly have 2 parts: > - T186 and later chips [1] > - T210 and prior chips [2] > > For [1] - Changes implemented to set pwm period dynamically and > also checks added to allow only if requested period(ns) is > below or equals to higher range. > > For [2] - Only checks if the requested period(ns) is below or equals > to higher range defined by max clock limit. The limitation > in T210 or prior chips are due to the reason of having only > one pwm-controller supporting multiple channels. But later > chips have multiple pwm controller instances each having > single channel support. > > Signed-off-by: Sandipan Patra <spa...@nvidia.com> > --- > PATCH V4: > 1. Code comments fixes > > PATCH V3: > 1. Return -EINVAL if requested period does not fall inside limit. > 2. Store the new clock rate for further references. > 3. Variable name change reverted. > 4. Comments corrected and new comments are added. > > PATCH V2: > 1. Maximum frequency calculation is moved to probe. > 2. Added descriptions for PWM register bits and functional behavior > of the controller when new configuration is applied. > 3. Setting period with possible value when supplied period is below limit. > 4. Corrected the earlier code comment: > plus 1 instead of minus 1 during pwm calculation > > drivers/pwm/pwm-tegra.c | 80 > ++++++++++++++++++++++++++++++++++++++++++++++--- > 1 file changed, 76 insertions(+), 4 deletions(-)
Applied, thanks. Thierry
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