Hi Piotr, Thank you for the patch! Yet something to improve:
[auto build test ERROR on pci/next] [also build test ERROR on mkp-scsi/for-next scsi/for-next linus/master v5.7 next-20200603] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Piotr-Stankiewicz/Forward-MSI-X-vector-enable-error-code-in-pci_alloc_irq_vectors_affinity/20200603-195246 base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next config: sh-allmodconfig (attached as .config) compiler: sh4-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=sh If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <l...@intel.com> All errors (new ones prefixed by >>, old ones prefixed by <<): drivers/crypto/inside-secure/safexcel.c:649:11: note: in expansion of macro 'GENMASK' 649 | GENMASK(priv->config.rings - 1, 0), | ^~~~~~~ include/linux/bits.h:26:28: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) | ^ arch/sh/include/asm/io.h:32:77: note: in definition of macro '__raw_writel' 32 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) | ^ arch/sh/include/asm/io.h:47:62: note: in expansion of macro 'ioswabl' 47 | #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) | ^~~~~~~ arch/sh/include/asm/io.h:57:32: note: in expansion of macro 'writel_relaxed' 57 | #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) | ^~~~~~~~~~~~~~ drivers/crypto/inside-secure/safexcel.c:757:3: note: in expansion of macro 'writel' 757 | writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), | ^~~~~~ include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( | ^~~~~~~~~~~~~~~~~ include/linux/bits.h:39:3: note: in expansion of macro 'GENMASK_INPUT_CHECK' 39 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) | ^~~~~~~~~~~~~~~~~~~ drivers/crypto/inside-secure/safexcel.c:757:35: note: in expansion of macro 'GENMASK' 757 | writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), | ^~~~~~~ include/linux/bits.h:26:40: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) | ^ arch/sh/include/asm/io.h:32:77: note: in definition of macro '__raw_writel' 32 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) | ^ arch/sh/include/asm/io.h:47:62: note: in expansion of macro 'ioswabl' 47 | #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) | ^~~~~~~ arch/sh/include/asm/io.h:57:32: note: in expansion of macro 'writel_relaxed' 57 | #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) | ^~~~~~~~~~~~~~ drivers/crypto/inside-secure/safexcel.c:757:3: note: in expansion of macro 'writel' 757 | writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), | ^~~~~~ include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( | ^~~~~~~~~~~~~~~~~ include/linux/bits.h:39:3: note: in expansion of macro 'GENMASK_INPUT_CHECK' 39 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) | ^~~~~~~~~~~~~~~~~~~ drivers/crypto/inside-secure/safexcel.c:757:35: note: in expansion of macro 'GENMASK' 757 | writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), | ^~~~~~~ include/linux/bits.h:26:28: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) | ^ arch/sh/include/asm/io.h:32:77: note: in definition of macro '__raw_writel' 32 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) | ^ arch/sh/include/asm/io.h:47:62: note: in expansion of macro 'ioswabl' 47 | #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) | ^~~~~~~ arch/sh/include/asm/io.h:57:32: note: in expansion of macro 'writel_relaxed' 57 | #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) | ^~~~~~~~~~~~~~ drivers/crypto/inside-secure/safexcel.c:761:3: note: in expansion of macro 'writel' 761 | writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), | ^~~~~~ include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( | ^~~~~~~~~~~~~~~~~ include/linux/bits.h:39:3: note: in expansion of macro 'GENMASK_INPUT_CHECK' 39 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) | ^~~~~~~~~~~~~~~~~~~ drivers/crypto/inside-secure/safexcel.c:761:35: note: in expansion of macro 'GENMASK' 761 | writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), | ^~~~~~~ include/linux/bits.h:26:40: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) | ^ arch/sh/include/asm/io.h:32:77: note: in definition of macro '__raw_writel' 32 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) | ^ arch/sh/include/asm/io.h:47:62: note: in expansion of macro 'ioswabl' 47 | #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) | ^~~~~~~ arch/sh/include/asm/io.h:57:32: note: in expansion of macro 'writel_relaxed' 57 | #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) | ^~~~~~~~~~~~~~ drivers/crypto/inside-secure/safexcel.c:761:3: note: in expansion of macro 'writel' 761 | writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), | ^~~~~~ include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( | ^~~~~~~~~~~~~~~~~ include/linux/bits.h:39:3: note: in expansion of macro 'GENMASK_INPUT_CHECK' 39 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) | ^~~~~~~~~~~~~~~~~~~ drivers/crypto/inside-secure/safexcel.c:761:35: note: in expansion of macro 'GENMASK' 761 | writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), | ^~~~~~~ drivers/crypto/inside-secure/safexcel.c: In function 'safexcel_probe_generic': << from drivers/crypto/inside-secure/safexcel.c:10: >> drivers/crypto/inside-secure/safexcel.c:1570:10: error: 'PCI_IRQ_MSI_TYPES' >> undeclared (first use in this function); did you mean 'PCI_IRQ_MSIX'? 1570 | PCI_IRQ_MSI_TYPES); | ^~~~~~~~~~~~~~~~~ | PCI_IRQ_MSIX drivers/crypto/inside-secure/safexcel.c:1570:10: note: each undeclared identifier is reported only once for each function it appears in vim +1570 drivers/crypto/inside-secure/safexcel.c 1382 1383 /* 1384 * Generic part of probe routine, shared by platform and PCI driver 1385 * 1386 * Assumes IO resources have been mapped, private data mem has been allocated, 1387 * clocks have been enabled, device pointer has been assigned etc. 1388 * 1389 */ 1390 static int safexcel_probe_generic(void *pdev, 1391 struct safexcel_crypto_priv *priv, 1392 int is_pci_dev) 1393 { 1394 struct device *dev = priv->dev; 1395 u32 peid, version, mask, val, hiaopt, hwopt, peopt; 1396 int i, ret, hwctg; 1397 1398 priv->context_pool = dmam_pool_create("safexcel-context", dev, 1399 sizeof(struct safexcel_context_record), 1400 1, 0); 1401 if (!priv->context_pool) 1402 return -ENOMEM; 1403 1404 /* 1405 * First try the EIP97 HIA version regs 1406 * For the EIP197, this is guaranteed to NOT return any of the test 1407 * values 1408 */ 1409 version = readl(priv->base + EIP97_HIA_AIC_BASE + EIP197_HIA_VERSION); 1410 1411 mask = 0; /* do not swap */ 1412 if (EIP197_REG_LO16(version) == EIP197_HIA_VERSION_LE) { 1413 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version); 1414 } else if (EIP197_REG_HI16(version) == EIP197_HIA_VERSION_BE) { 1415 /* read back byte-swapped, so complement byte swap bits */ 1416 mask = EIP197_MST_CTRL_BYTE_SWAP_BITS; 1417 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version); 1418 } else { 1419 /* So it wasn't an EIP97 ... maybe it's an EIP197? */ 1420 version = readl(priv->base + EIP197_HIA_AIC_BASE + 1421 EIP197_HIA_VERSION); 1422 if (EIP197_REG_LO16(version) == EIP197_HIA_VERSION_LE) { 1423 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version); 1424 priv->flags |= SAFEXCEL_HW_EIP197; 1425 } else if (EIP197_REG_HI16(version) == 1426 EIP197_HIA_VERSION_BE) { 1427 /* read back byte-swapped, so complement swap bits */ 1428 mask = EIP197_MST_CTRL_BYTE_SWAP_BITS; 1429 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version); 1430 priv->flags |= SAFEXCEL_HW_EIP197; 1431 } else { 1432 return -ENODEV; 1433 } 1434 } 1435 1436 /* Now initialize the reg offsets based on the probing info so far */ 1437 safexcel_init_register_offsets(priv); 1438 1439 /* 1440 * If the version was read byte-swapped, we need to flip the device 1441 * swapping Keep in mind here, though, that what we write will also be 1442 * byte-swapped ... 1443 */ 1444 if (mask) { 1445 val = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); 1446 val = val ^ (mask >> 24); /* toggle byte swap bits */ 1447 writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); 1448 } 1449 1450 /* 1451 * We're not done probing yet! We may fall through to here if no HIA 1452 * was found at all. So, with the endianness presumably correct now and 1453 * the offsets setup, *really* probe for the EIP97/EIP197. 1454 */ 1455 version = readl(EIP197_GLOBAL(priv) + EIP197_VERSION); 1456 if (((priv->flags & SAFEXCEL_HW_EIP197) && 1457 (EIP197_REG_LO16(version) != EIP197_VERSION_LE) && 1458 (EIP197_REG_LO16(version) != EIP196_VERSION_LE)) || 1459 ((!(priv->flags & SAFEXCEL_HW_EIP197) && 1460 (EIP197_REG_LO16(version) != EIP97_VERSION_LE)))) { 1461 /* 1462 * We did not find the device that matched our initial probing 1463 * (or our initial probing failed) Report appropriate error. 1464 */ 1465 dev_err(priv->dev, "Probing for EIP97/EIP19x failed - no such device (read %08x)\n", 1466 version); 1467 return -ENODEV; 1468 } 1469 1470 priv->hwconfig.hwver = EIP197_VERSION_MASK(version); 1471 hwctg = version >> 28; 1472 peid = version & 255; 1473 1474 /* Detect EIP206 processing pipe */ 1475 version = readl(EIP197_PE(priv) + + EIP197_PE_VERSION(0)); 1476 if (EIP197_REG_LO16(version) != EIP206_VERSION_LE) { 1477 dev_err(priv->dev, "EIP%d: EIP206 not detected\n", peid); 1478 return -ENODEV; 1479 } 1480 priv->hwconfig.ppver = EIP197_VERSION_MASK(version); 1481 1482 /* Detect EIP96 packet engine and version */ 1483 version = readl(EIP197_PE(priv) + EIP197_PE_EIP96_VERSION(0)); 1484 if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) { 1485 dev_err(dev, "EIP%d: EIP96 not detected.\n", peid); 1486 return -ENODEV; 1487 } 1488 priv->hwconfig.pever = EIP197_VERSION_MASK(version); 1489 1490 hwopt = readl(EIP197_GLOBAL(priv) + EIP197_OPTIONS); 1491 hiaopt = readl(EIP197_HIA_AIC(priv) + EIP197_HIA_OPTIONS); 1492 1493 if (priv->flags & SAFEXCEL_HW_EIP197) { 1494 /* EIP197 */ 1495 peopt = readl(EIP197_PE(priv) + EIP197_PE_OPTIONS(0)); 1496 1497 priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) & 1498 EIP197_HWDATAW_MASK; 1499 priv->hwconfig.hwcfsize = ((hiaopt >> EIP197_CFSIZE_OFFSET) & 1500 EIP197_CFSIZE_MASK) + 1501 EIP197_CFSIZE_ADJUST; 1502 priv->hwconfig.hwrfsize = ((hiaopt >> EIP197_RFSIZE_OFFSET) & 1503 EIP197_RFSIZE_MASK) + 1504 EIP197_RFSIZE_ADJUST; 1505 priv->hwconfig.hwnumpes = (hiaopt >> EIP197_N_PES_OFFSET) & 1506 EIP197_N_PES_MASK; 1507 priv->hwconfig.hwnumrings = (hiaopt >> EIP197_N_RINGS_OFFSET) & 1508 EIP197_N_RINGS_MASK; 1509 if (hiaopt & EIP197_HIA_OPT_HAS_PE_ARB) 1510 priv->flags |= EIP197_PE_ARB; 1511 if (EIP206_OPT_ICE_TYPE(peopt) == 1) 1512 priv->flags |= EIP197_ICE; 1513 /* If not a full TRC, then assume simple TRC */ 1514 if (!(hwopt & EIP197_OPT_HAS_TRC)) 1515 priv->flags |= EIP197_SIMPLE_TRC; 1516 /* EIP197 always has SOME form of TRC */ 1517 priv->flags |= EIP197_TRC_CACHE; 1518 } else { 1519 /* EIP97 */ 1520 priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) & 1521 EIP97_HWDATAW_MASK; 1522 priv->hwconfig.hwcfsize = (hiaopt >> EIP97_CFSIZE_OFFSET) & 1523 EIP97_CFSIZE_MASK; 1524 priv->hwconfig.hwrfsize = (hiaopt >> EIP97_RFSIZE_OFFSET) & 1525 EIP97_RFSIZE_MASK; 1526 priv->hwconfig.hwnumpes = 1; /* by definition */ 1527 priv->hwconfig.hwnumrings = (hiaopt >> EIP197_N_RINGS_OFFSET) & 1528 EIP197_N_RINGS_MASK; 1529 } 1530 1531 /* Scan for ring AIC's */ 1532 for (i = 0; i < EIP197_MAX_RING_AIC; i++) { 1533 version = readl(EIP197_HIA_AIC_R(priv) + 1534 EIP197_HIA_AIC_R_VERSION(i)); 1535 if (EIP197_REG_LO16(version) != EIP201_VERSION_LE) 1536 break; 1537 } 1538 priv->hwconfig.hwnumraic = i; 1539 /* Low-end EIP196 may not have any ring AIC's ... */ 1540 if (!priv->hwconfig.hwnumraic) { 1541 dev_err(priv->dev, "No ring interrupt controller present!\n"); 1542 return -ENODEV; 1543 } 1544 1545 /* Get supported algorithms from EIP96 transform engine */ 1546 priv->hwconfig.algo_flags = readl(EIP197_PE(priv) + 1547 EIP197_PE_EIP96_OPTIONS(0)); 1548 1549 /* Print single info line describing what we just detected */ 1550 dev_info(priv->dev, "EIP%d:%x(%d,%d,%d,%d)-HIA:%x(%d,%d,%d),PE:%x/%x,alg:%08x\n", 1551 peid, priv->hwconfig.hwver, hwctg, priv->hwconfig.hwnumpes, 1552 priv->hwconfig.hwnumrings, priv->hwconfig.hwnumraic, 1553 priv->hwconfig.hiaver, priv->hwconfig.hwdataw, 1554 priv->hwconfig.hwcfsize, priv->hwconfig.hwrfsize, 1555 priv->hwconfig.ppver, priv->hwconfig.pever, 1556 priv->hwconfig.algo_flags); 1557 1558 safexcel_configure(priv); 1559 1560 if (IS_ENABLED(CONFIG_PCI) && priv->version == EIP197_DEVBRD) { 1561 /* 1562 * Request MSI vectors for global + 1 per ring - 1563 * or just 1 for older dev images 1564 */ 1565 struct pci_dev *pci_pdev = pdev; 1566 1567 ret = pci_alloc_irq_vectors(pci_pdev, 1568 priv->config.rings + 1, 1569 priv->config.rings + 1, > 1570 PCI_IRQ_MSI_TYPES); 1571 if (ret < 0) { 1572 dev_err(dev, "Failed to allocate PCI MSI interrupts\n"); 1573 return ret; 1574 } 1575 } 1576 1577 /* Register the ring IRQ handlers and configure the rings */ 1578 priv->ring = devm_kcalloc(dev, priv->config.rings, 1579 sizeof(*priv->ring), 1580 GFP_KERNEL); 1581 if (!priv->ring) 1582 return -ENOMEM; 1583 1584 for (i = 0; i < priv->config.rings; i++) { 1585 char wq_name[9] = {0}; 1586 int irq; 1587 struct safexcel_ring_irq_data *ring_irq; 1588 1589 ret = safexcel_init_ring_descriptors(priv, 1590 &priv->ring[i].cdr, 1591 &priv->ring[i].rdr); 1592 if (ret) { 1593 dev_err(dev, "Failed to initialize rings\n"); 1594 return ret; 1595 } 1596 1597 priv->ring[i].rdr_req = devm_kcalloc(dev, 1598 EIP197_DEFAULT_RING_SIZE, 1599 sizeof(priv->ring[i].rdr_req), 1600 GFP_KERNEL); 1601 if (!priv->ring[i].rdr_req) 1602 return -ENOMEM; 1603 1604 ring_irq = devm_kzalloc(dev, sizeof(*ring_irq), GFP_KERNEL); 1605 if (!ring_irq) 1606 return -ENOMEM; 1607 1608 ring_irq->priv = priv; 1609 ring_irq->ring = i; 1610 1611 irq = safexcel_request_ring_irq(pdev, 1612 EIP197_IRQ_NUMBER(i, is_pci_dev), 1613 is_pci_dev, 1614 safexcel_irq_ring, 1615 safexcel_irq_ring_thread, 1616 ring_irq); 1617 if (irq < 0) { 1618 dev_err(dev, "Failed to get IRQ ID for ring %d\n", i); 1619 return irq; 1620 } 1621 1622 priv->ring[i].work_data.priv = priv; 1623 priv->ring[i].work_data.ring = i; 1624 INIT_WORK(&priv->ring[i].work_data.work, 1625 safexcel_dequeue_work); 1626 1627 snprintf(wq_name, 9, "wq_ring%d", i); 1628 priv->ring[i].workqueue = 1629 create_singlethread_workqueue(wq_name); 1630 if (!priv->ring[i].workqueue) 1631 return -ENOMEM; 1632 1633 priv->ring[i].requests = 0; 1634 priv->ring[i].busy = false; 1635 1636 crypto_init_queue(&priv->ring[i].queue, 1637 EIP197_DEFAULT_RING_SIZE); 1638 1639 spin_lock_init(&priv->ring[i].lock); 1640 spin_lock_init(&priv->ring[i].queue_lock); 1641 } 1642 1643 atomic_set(&priv->ring_used, 0); 1644 1645 ret = safexcel_hw_init(priv); 1646 if (ret) { 1647 dev_err(dev, "HW init failed (%d)\n", ret); 1648 return ret; 1649 } 1650 1651 ret = safexcel_register_algorithms(priv); 1652 if (ret) { 1653 dev_err(dev, "Failed to register algorithms (%d)\n", ret); 1654 return ret; 1655 } 1656 1657 return 0; 1658 } 1659 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
